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%%           |_| |_| \_____|  \__| |____| microLab                            %%
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%%                                                                            %%
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%%           Bern University of Applied Sciences (BFH)                        %%
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%%           Quellgasse 21                                                    %%
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%%           Room HG 4.33                                                     %%
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%%           2501 Biel/Bienne                                                 %%
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%%           Switzerland                                                      %%
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%%           http://www.microlab.ch                                           %%
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\chapter{Input and Output}
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\label{chap:IO}
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The {\sc GECKO4com} provides input and output functionality by the
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implementation of a VGA controller, button and switches, LEDs, and a RS232
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pass-through. Each of these IO components will be discussed in this chapter.
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%-----------------------------------------------------------------------------
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\section{VGA controller}
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\label{sec: vga}
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The VGA controller provides a VGA screen at the resolution of 1024x768 by a
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refresh rate of 60Hz. The screen can only display ASCII characters (so no
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graphical mode is provided) and is divided into three display areas (see
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Appendix~\ref{appen:4com}). The screen uses a simple 8-color palette as shown in
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Figure~\ref{fig:vga color}.
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\begin{figure}[hb]
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\centering%
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\includegraphics[width=0.6\columnwidth]{figs/vga_colors}
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\caption{The color palette as used by the VGA controller. The numbers above the
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colors indicate the index for the foreground or background color.}
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\label{fig:vga color}
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\end{figure}
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The VGA controller provides a 7-bit {\sc ASCII} table. As all implemented
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commands use a byte to put characters on the screen, the $8^{\text{th}}$ bit is
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used for color inversion. If the $8^{\text{th}}$ bit equals to \verb+0+ the character
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pixels are displayed in the foreground color and the rest is displayed in the
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background color. If the $8^{\text{th}}$ bit equals to \verb+1+ the character
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pixels are displayed in the background color and the rest is displayed in the
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foreground color. Each character consists of 16 lines each containing 8 pixels.
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The three screens provided by the VGA controller are described below.
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\begin{itemize}
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\item \textbf{Static User Window (SUW).} This window displays a static contents
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that is stored in the non-volatile memory of the {\sc GECKO4com}. The colors of
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this window are fixed to a background color black (\verb+0+) and a foreground
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color white (\verb+7+). The contents of this screen can be changed by the
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\verb+*PUD+ command described in Chapter~\ref{sec: PUD}.
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\item \textbf{USBTMC Message Window(UMW).} This window can be controlled by the
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\verb+VGA:+ SCPI commandos described in Chapter~\ref{sec: vga commands}. At
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startup the {\sc GECKO4com} initializes the foreground color to white (\verb+7+)
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and the background color to black (\verb+0+). The cursor is always displayed and
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blinks with a frequency of 1~Hz. This window scrolls automatically when the
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cursor reaches the end of the screen; however, no scroll-back buffer is
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provided.
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\item \textbf{User FPGA Message Window (FMW).} This window can be controlled by the
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the memory mapped registers described in Chapter~\ref{sec:mem map}. At
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startup the {\sc GECKO4com} initializes the foreground color to red (\verb+4+)
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and the background color to black (\verb+0+). The cursor is always displayed and
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blinks with a frequency of 1~Hz. This window scrolls automatically when the
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cursor reaches the end of the screen; however, no scroll-back buffer is
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provided.
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\end{itemize}
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%-----------------------------------------------------------------------------
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\section{Buttons, Switch and LEDs}
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\label{sec:but switch}
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The {\sc GECKO4com} provides three general purpose buttons and one hexswitch
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(see Appendix~\ref{appen:4com}). The hexswitch can be manipulated by USBTMC
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commandos (see Chapter~\ref{sec: hexswitch}) and read out by the user FPGA
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through a memory mapped register (see Chapter~\ref{sec:mem map}). When reading
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the register at address \verb+0x27+ the current value of the hexswitch is
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returned in the lower 4 bits of the register. The resting bits are set to 0.
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The state of the buttons can only be read out by the user FPGA through a memory
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mapped register (see Chapter~\ref{sec:mem map}). When reading the register at
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address \verb+0x26+ the current state of the buttons is returned. The current
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state is \verb+0+ when the button is not pressed and \verb+1+ otherwise. The
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{\sc GECKO4com} returns the state of {\sc button1} in bit 0, {\sc button2} in
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bit 1, and {\sc button3} in bit 2. All the other bits of this register are set
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to 0.\\
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\textit{Note: {\sc button3} has a special functionality; if this button is
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pressed during power-on or during board reset the FX2 is prevented to load its
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firmware stored in the {\sc GECKO4com}'s non-volatile memory.}\\
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Besides the buttons and the switch, the {\sc GECKO4com} also controls eight
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bi-color LEDs. During normal operation these LEDs can be controlled by the user
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FPGA through memory mapped registers (see Chapter~\ref{sec:mem map}). Each LED
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has a 4-bit control register. The values that can be written to these control
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registers and the operation of the LED is listed in Table~\ref{tab:led cntrl}.
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\begin{table}[t]
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\centering%
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\begin{tabular}{|c|l|}
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\hline
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\textbf{Value}&\textbf{LED function}\\
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\hline
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\hline
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\verb+0x0+&LED is off\\
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\hline
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\verb+0x1+&LED is off\\
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\hline
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\verb+0x2+&LED is continues red\\
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\hline
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\verb+0x3+&LED is continues green\\
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\hline
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\verb+0x4+&LED is slowly blinking red\\
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\hline
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\verb+0x5+&LED is slowly blinking green\\
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\hline
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\verb+0x6+&LED is slowly toggling red-green\\
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\hline
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\verb+0x7+&LED is slowly toggling red-green\\
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\hline
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\verb+0x8+&LED is off\\
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\hline
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\verb+0x9+&LED is off\\
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\hline
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\verb+0xA+&LED is continues red\\
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\hline
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\verb+0xB+&LED is continues green\\
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\hline
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\verb+0xC+&LED is fast blinking red\\
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\hline
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\verb+0xD+&LED is fast blinking green\\
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\hline
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\verb+0xE+&LED is fast toggling red-green\\
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\hline
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\verb+0xF+&LED is fast toggling red-green\\
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\hline
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\end{tabular}
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\caption{Values and function of the memory-mapped LED control register.}
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\label{tab:led cntrl}
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\end{table}
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There are two situation in which the LEDs are controlled by the {\sc GECKO4com}:
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\begin{enumerate}
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\item In case of an identification command the LEDs light up as described in
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Chapter~\ref{sec: main info}.
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\item If the {\sc GECKO4com} is busy and cannot accept new command (for example during the erase of the non-volatile
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memory), the LED7 will light up red and the other LEDs will be off.
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\end{enumerate}
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%-----------------------------------------------------------------------------
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\section{RS232 pass-through}
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The {\sc GECKO4com} provides two signals that are put on the external connector
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and can be used for example as carriers for a RS232 communication protocol. The
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signals on the connector are {\sc lvttl} whilst the signals on the user FPGA are
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{\sc lvcmos25}. Table~\ref{tab:rs232} shows the signals and their pin on the user FPGA.
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\begin{table}[h]
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\centering%
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\begin{tabular}{|l|l|l|}
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\hline
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\textbf{Name}&\textbf{Direction}&\textbf{Pin}\\
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\hline
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\hline
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RS232TxD&{\sc output}&\verb+AF13+\\
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\hline
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RS232RxD&{\sc input}&\verb+Y16+\\
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\hline
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\end{tabular}
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\caption{RS232 communication lines as provided on the user FPGA. Both these
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signals are {\sc lvcmos25}.}
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\label{tab:rs232}
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\end{table}
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%-----------------------------------------------------------------------------
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\section{User clocks}
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The {\sc genio1} connector on the {\sc GECKO4main} provides two user clocks.
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These clocks are connected to the {\sc GECKO4com} for level adaptation. In the
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{\sc GECKO4com} these two clocks are put on a Digital Loop Lock (DLL) for timing
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compensation. The {\sc GECKO4com} provides the user clocks including a lock
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signal to the user FPGA. If the lock signal is \verb+0+ the clocks should not be
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used, and if the lock signal is \verb+1+ the clock is stable and locked by the
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{\sc GECKO4com}. The DLL used in the {\sc GECKO4com} poses some restriction on
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the user clocks. The restriction is the frequency range a user clock is allowed
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to have. The user clocks must be in the range of [18MHz...167MHz] with a duty
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cycle in between 40\% and 60\%. Table~\ref{tab:clocks} list the connections to the user
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FPGA.
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\begin{table}[h]
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\centering%
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\begin{tabular}{|l|l||l|l|}
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\hline
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\textbf{Signal}&\textbf{Pin}&
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\textbf{Signal}&\textbf{Pin}\\
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\hline
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\hline
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User Clock 1&\verb+AF14+&User Lock 1&\verb+AA9+\\
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\hline
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User Clock 2&\verb+AE14+&User Lock 2&\verb+AB9+\\
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\hline
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\end{tabular}
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\caption{User Clock and User Lock signals on the user FPGA. All signals are {\sc
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inputs} and of type {\sc lvcmos25}.}
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\label{tab:clocks}
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\end{table}

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