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[/] [nocem/] [trunk/] [VHDL/] [fifo_gfs.vhd] - Blame information for rev 8

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-----------------------------------------------------------------------------
-- NoCem -- Network on Chip Emulation Tool for System on Chip Research 
-- and Implementations
-- 
-- Copyright (C) 2006  Graham Schelle, Dirk Grunwald
-- 
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
-- 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
-- 
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  
-- 02110-1301, USA.
-- 
-- The authors can be contacted by email: <schelleg,grunwald>@cs.colorado.edu 
-- 
-- or by mail: Campus Box 430, Department of Computer Science,
-- University of Colorado at Boulder, Boulder, Colorado 80309
-------------------------------------------------------------------------------- 
 
 
-- 
-- Filename: fifo_gfs.vhd
-- 
-- Description: an all vhdl version of a FIFO
-- 
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity fifo_gfs is
        generic (
                WIDTH : integer := 16;          -- FIFO word width
                ADD_WIDTH : integer := 3        -- Address Width
                );
 
        PORT(
                Data_in : IN std_logic_vector(WIDTH-1 downto 0);
                clk : IN std_logic;
                Reset : IN std_logic;
                RE : IN std_logic;
                WE : IN std_logic;
                Data_out : OUT std_logic_vector(WIDTH-1 downto 0);
                Full : OUT std_logic;
                Half_full : OUT std_logic;
                empty : OUT std_logic
                );
end fifo_gfs;
 
 
 
architecture Behavioral of fifo_gfs is
 
        signal MAX_ADDR:  std_logic_vector(ADD_WIDTH   downto 0);
        signal MIN_ADDR:  std_logic_vector(ADD_WIDTH   downto 0);
 
 
    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);
         signal D_ADD   : std_logic_vector(ADD_WIDTH     downto 0);       -- notice size of ADD_WIDTH+1
 
 
         signal rst_n : std_logic;
 
         signal empty_datain,empty_dataout,empty_memcore : std_logic;
         signal full_datain,full_dataout,full_memcore    : std_logic;
 
         signal dout_dataout,dout_datain,dout_memcore : std_logic_vector(WIDTH-1 downto 0);
         signal din_dataout,din_datain,din_memcore : std_logic_vector(WIDTH-1 downto 0);
         signal we_dataout,we_datain,we_memcore : std_logic;
         signal re_dataout,re_datain,re_memcore : std_logic;
 
        component dpmem
            generic (ADD_WIDTH : integer;
                                 WIDTH : integer);
 
        port (clk : in std_logic;
            reset : in std_logic;
                w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
            r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
            data_in : in std_logic_vector(WIDTH - 1 downto 0);
            data_out : out std_logic_vector(WIDTH - 1 downto 0 );
            WR  : in std_logic;
            RE  : in std_logic);
        end component;
 
        COMPONENT fifo_reg
        generic (
                WIDTH : integer
        );
        PORT(
                clk : IN std_logic;
                din : IN std_logic_vector(WIDTH-1 downto 0);
                rd_en : IN std_logic;
                rst : IN std_logic;
                wr_en : IN std_logic;
                dout : OUT std_logic_vector(WIDTH-1 downto 0);
                empty : OUT std_logic;
                full : OUT std_logic
                );
        END COMPONENT;
 
 
begin
 
 
        constant_sigs : process (empty_datain,empty_memcore, empty_dataout, full_datain, full_memcore, full_dataout, Reset)
        begin
                empty <=  empty_datain and empty_memcore and empty_dataout;
                full  <=  full_datain  and full_memcore  and full_dataout;
                Half_full <= '0';
 
                rst_n <= not reset;
 
 
                MAX_ADDR <= (others => '0');
                MAX_ADDR(ADD_WIDTH) <= '1';
                MIN_ADDR <= (others => '0');
 
        end process;
 
 
        -----------------------------------------------------------
        ------------------- SIGNAL GENERATION ---------------------
        -----------------------------------------------------------
 
        -- dataout_fifo
        Data_out   <= dout_dataout;
 
 
        dataflow_gen : process (dout_memcore, dout_datain,full_dataout,WE, Data_in, full_memcore, full_datain, RE, empty_memcore, empty_datain)
        begin
 
 
                din_dataout <= (others => '0');
                we_dataout      <= '0';
                re_dataout      <= '0';
 
                din_memcore <= (others => '0');
                we_memcore      <= '0';
                re_memcore      <= '0';
 
                din_datain  <= (others => '0');
                we_datain       <= '0';
                re_datain       <= '0';
 
 
 
                -- where to do writing of new data
                if full_dataout='0' and WE='1' and RE='0' then
                        din_dataout     <= Data_in;
                        we_dataout  <= WE;
                elsif   full_memcore='0' and WE='1' and RE='0' then
                        din_memcore     <= Data_in;
                        we_memcore  <= WE;
                elsif full_datain='0' and WE='1' and RE='0' then
                        din_datain      <= Data_in;
                        we_datain  <= WE;
                end if;
 
                -- handling RE's
                if RE='1' and WE='0' then
                        re_dataout <= RE;
 
                        if empty_memcore='0' then
                                re_memcore <= '1';
                                we_dataout <= '1';
                                din_dataout <= dout_memcore;
                        end if;
 
                        if empty_datain='0' then
                                re_datain  <= '1';
                                we_memcore <= '1';
                                din_memcore <= dout_datain;
                        end if;
                end if;
 
 
                if RE='1' and WE='1' then
 
                        if full_dataout='1' and empty_memcore='1' then
                                re_dataout <= '1';
                                we_dataout <= '1';
                                din_dataout <= data_in;
                        elsif full_dataout='1' and empty_memcore='0' and empty_datain='1' then
                                re_dataout <= '1';
                                re_memcore <= '1';
                                we_dataout <= '1';
                                we_memcore <= '1';
                                din_dataout <= dout_memcore;
                           din_memcore <= data_in;
                        elsif full_dataout='1' and full_memcore='1' and full_datain='1' then
                                re_dataout <= '1';
                                re_memcore <= '1';
                                we_dataout <= '1';
                                we_memcore <= '1';
                                re_datain  <= '1';
                                we_datain  <= '1';
                                din_dataout  <= dout_memcore;
                           din_memcore <= dout_datain;
                                din_datain   <= data_in;
                        end if;
                end if;
 
 
 
        end process;
 
 
 
 
        -- handling memcore signalling
        memcore_sig_gen_clkd : process (clk,reset)
        begin
 
                if reset='1' then
                        W_ADD <= (others =>'0');
                        R_ADD <= (others =>'0');
                        D_ADD <= (others =>'0');
                elsif clk='1' and clk'event then
 
                        if we_memcore = '1' then
                                W_ADD <= W_ADD + 1;
                        end if;
 
                        if re_memcore = '1' then
                           R_ADD <= R_ADD + 1;
                   end if;
 
                        if we_memcore='1' and re_memcore='1' then
                                null;
                        elsif we_memcore='1' then
                                D_ADD <= D_ADD + 1;
                        elsif re_memcore='1' then
                                D_ADD <= D_ADD - 1;
                        else
                                null;
                        end if;
 
                end if;
 
        end process;
 
 
        -- handling memcore signalling
        memcore_sig_gen_uclkd : process (D_ADD, MIN_ADDR, MAX_ADDR)
        begin
 
                        if D_ADD = MIN_ADDR then
                                empty_memcore <= '1';
                        else
                                empty_memcore <= '0';
                        end if;
 
                        if D_ADD = MAX_ADDR then
                                full_memcore <= '1';
                        else
                                full_memcore <= '0';
                        end if;
 
        end process;
 
 
        -----------------------------------------------------------
        ------------------- THE ACTUAL FIFOS ----------------------
        -----------------------------------------------------------
 
        datain_reg : fifo_reg
        Generic map(
                WIDTH => WIDTH
        )
        PORT MAP(
                clk => clk,
                din => din_datain,
                rd_en => re_datain,
                rst => Reset,
                wr_en => we_datain,
                dout => dout_datain,
                empty => empty_datain,
                full => full_datain
        );
 
 
        memcore: dpmem
        generic map (
                                ADD_WIDTH =>ADD_WIDTH,
                                WIDTH => WIDTH
                                )
        port map (clk => clk,
                         reset => rst_n,
                         w_add => W_ADD,
                         r_add => R_ADD,
                         Data_in => din_memcore,
                         data_out => dout_memcore,
                         wr => we_memcore,
                         re => re_memcore);
 
 
        dataout_reg : fifo_reg
        Generic map(
                WIDTH => WIDTH
        )
        PORT MAP(
                clk => clk,
                din => din_dataout,
                rd_en => re_dataout,
                rst => reset,
                wr_en => we_dataout,
                dout => dout_dataout,
                empty => empty_dataout,
                full => full_dataout
        );
 
 
 
 
end Behavioral;

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[/] [nocem/] [trunk/] [VHDL/] [fifo_gfs.vhd] - Blame information for rev 8

Line No.	Rev	Author	Line
1	4	schelleg
2			`-----------------------------------------------------------------------------`
3			`-- NoCem -- Network on Chip Emulation Tool for System on Chip Research`
4			`-- and Implementations`
5			`--`
6			`-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald`
7			`--`
8			`-- This program is free software; you can redistribute it and/or`
9			`-- modify it under the terms of the GNU General Public License`
10			`-- as published by the Free Software Foundation; either version 2`
11			`-- of the License, or (at your option) any later version.`
12			`--`
13			`-- This program is distributed in the hope that it will be useful,`
14			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`-- GNU General Public License for more details.`
17			`--`
18			`-- You should have received a copy of the GNU General Public License`
19			`-- along with this program; if not, write to the Free Software`
20			`-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA`
21			`-- 02110-1301, USA.`
22			`--`
23			`-- The authors can be contacted by email: <schelleg,grunwald>@cs.colorado.edu`
24			`--`
25			`-- or by mail: Campus Box 430, Department of Computer Science,`
26			`-- University of Colorado at Boulder, Boulder, Colorado 80309`
27			`--------------------------------------------------------------------------------`
28
29
30			`--`
31	2	schelleg	`-- Filename: fifo_gfs.vhd`
32	4	schelleg	`--`
33	2	schelleg	`-- Description: an all vhdl version of a FIFO`
34	4	schelleg	`--`
35
36
37
38			`library IEEE;`
39			`use IEEE.STD_LOGIC_1164.ALL;`
40			`use IEEE.STD_LOGIC_ARITH.ALL;`
41			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
42
43			`entity fifo_gfs is`
44	2	schelleg	`generic (`
45			`WIDTH : integer := 16; -- FIFO word width`
46			`ADD_WIDTH : integer := 3 -- Address Width`
47			`);`
48
49			`PORT(`
50			`Data_in : IN std_logic_vector(WIDTH-1 downto 0);`
51			`clk : IN std_logic;`
52			`Reset : IN std_logic;`
53			`RE : IN std_logic;`
54			`WE : IN std_logic;`
55			`Data_out : OUT std_logic_vector(WIDTH-1 downto 0);`
56			`Full : OUT std_logic;`
57			`Half_full : OUT std_logic;`
58			`empty : OUT std_logic`
59	4	schelleg	`);`
60			`end fifo_gfs;`
61	2	schelleg
62	4	schelleg
63
64			`architecture Behavioral of fifo_gfs is`
65
66			`signal MAX_ADDR: std_logic_vector(ADD_WIDTH downto 0);`
67			`signal MIN_ADDR: std_logic_vector(ADD_WIDTH downto 0);`
68
69
70	2	schelleg	`signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address`
71			`signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0);`
72	4	schelleg	`signal D_ADD : std_logic_vector(ADD_WIDTH downto 0); -- notice size of ADD_WIDTH+1`
73
74
75			`signal rst_n : std_logic;`
76
77			`signal empty_datain,empty_dataout,empty_memcore : std_logic;`
78			`signal full_datain,full_dataout,full_memcore : std_logic;`
79
80			`signal dout_dataout,dout_datain,dout_memcore : std_logic_vector(WIDTH-1 downto 0);`
81			`signal din_dataout,din_datain,din_memcore : std_logic_vector(WIDTH-1 downto 0);`
82			`signal we_dataout,we_datain,we_memcore : std_logic;`
83			`signal re_dataout,re_datain,re_memcore : std_logic;`
84
85	2	schelleg	`component dpmem`
86			`generic (ADD_WIDTH : integer;`
87			`WIDTH : integer);`
88
89			`port (clk : in std_logic;`
90			`reset : in std_logic;`
91			`w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );`
92			`r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );`
93			`data_in : in std_logic_vector(WIDTH - 1 downto 0);`
94			`data_out : out std_logic_vector(WIDTH - 1 downto 0 );`
95			`WR : in std_logic;`
96			`RE : in std_logic);`
97	4	schelleg	`end component;`
98
99			`COMPONENT fifo_reg`
100	2	schelleg	`generic (`
101	4	schelleg	`WIDTH : integer`
102			`);`
103			`PORT(`
104			`clk : IN std_logic;`
105			`din : IN std_logic_vector(WIDTH-1 downto 0);`
106			`rd_en : IN std_logic;`
107			`rst : IN std_logic;`
108			`wr_en : IN std_logic;`
109			`dout : OUT std_logic_vector(WIDTH-1 downto 0);`
110			`empty : OUT std_logic;`
111			`full : OUT std_logic`
112			`);`
113			`END COMPONENT;`
114
115
116			`begin`
117
118
119			`constant_sigs : process (empty_datain,empty_memcore, empty_dataout, full_datain, full_memcore, full_dataout, Reset)`
120			`begin`
121			`empty <= empty_datain and empty_memcore and empty_dataout;`
122			`full <= full_datain and full_memcore and full_dataout;`
123			`Half_full <= '0';`
124
125			`rst_n <= not reset;`
126
127
128			`MAX_ADDR <= (others => '0');`
129			`MAX_ADDR(ADD_WIDTH) <= '1';`
130			`MIN_ADDR <= (others => '0');`
131
132			`end process;`
133
134
135			`-----------------------------------------------------------`
136			`------------------- SIGNAL GENERATION ---------------------`
137			`-----------------------------------------------------------`
138
139			`-- dataout_fifo`
140			`Data_out <= dout_dataout;`
141
142
143			`dataflow_gen : process (dout_memcore, dout_datain,full_dataout,WE, Data_in, full_memcore, full_datain, RE, empty_memcore, empty_datain)`
144			`begin`
145
146
147			`din_dataout <= (others => '0');`
148			`we_dataout <= '0';`
149			`re_dataout <= '0';`
150
151			`din_memcore <= (others => '0');`
152			`we_memcore <= '0';`
153			`re_memcore <= '0';`
154
155			`din_datain <= (others => '0');`
156			`we_datain <= '0';`
157			`re_datain <= '0';`
158
159
160
161			`-- where to do writing of new data`
162			`if full_dataout='0' and WE='1' and RE='0' then`
163			`din_dataout <= Data_in;`
164			`we_dataout <= WE;`
165			`elsif full_memcore='0' and WE='1' and RE='0' then`
166			`din_memcore <= Data_in;`
167			`we_memcore <= WE;`
168			`elsif full_datain='0' and WE='1' and RE='0' then`
169			`din_datain <= Data_in;`
170			`we_datain <= WE;`
171			`end if;`
172
173			`-- handling RE's`
174			`if RE='1' and WE='0' then`
175			`re_dataout <= RE;`
176
177			`if empty_memcore='0' then`
178			`re_memcore <= '1';`
179			`we_dataout <= '1';`
180			`din_dataout <= dout_memcore;`
181			`end if;`
182
183			`if empty_datain='0' then`
184			`re_datain <= '1';`
185			`we_memcore <= '1';`
186			`din_memcore <= dout_datain;`
187			`end if;`
188			`end if;`
189
190
191			`if RE='1' and WE='1' then`
192
193			`if full_dataout='1' and empty_memcore='1' then`
194			`re_dataout <= '1';`
195			`we_dataout <= '1';`
196			`din_dataout <= data_in;`
197			`elsif full_dataout='1' and empty_memcore='0' and empty_datain='1' then`
198			`re_dataout <= '1';`
199			`re_memcore <= '1';`
200			`we_dataout <= '1';`
201			`we_memcore <= '1';`
202			`din_dataout <= dout_memcore;`
203			`din_memcore <= data_in;`
204			`elsif full_dataout='1' and full_memcore='1' and full_datain='1' then`
205			`re_dataout <= '1';`
206			`re_memcore <= '1';`
207			`we_dataout <= '1';`
208			`we_memcore <= '1';`
209			`re_datain <= '1';`
210			`we_datain <= '1';`
211			`din_dataout <= dout_memcore;`
212			`din_memcore <= dout_datain;`
213			`din_datain <= data_in;`
214			`end if;`
215			`end if;`
216
217
218
219			`end process;`
220
221
222
223
224			`-- handling memcore signalling`
225			`memcore_sig_gen_clkd : process (clk,reset)`
226			`begin`
227
228			`if reset='1' then`
229	2	schelleg	`W_ADD <= (others =>'0');`
230			`R_ADD <= (others =>'0');`
231	4	schelleg	`D_ADD <= (others =>'0');`
232			`elsif clk='1' and clk'event then`
233
234	2	schelleg	`if we_memcore = '1' then`
235			`W_ADD <= W_ADD + 1;`
236	4	schelleg	`end if;`
237
238	2	schelleg	`if re_memcore = '1' then`
239			`R_ADD <= R_ADD + 1;`
240	4	schelleg	`end if;`
241
242	2	schelleg	`if we_memcore='1' and re_memcore='1' then`
243			`null;`
244			`elsif we_memcore='1' then`
245			`D_ADD <= D_ADD + 1;`
246			`elsif re_memcore='1' then`
247			`D_ADD <= D_ADD - 1;`
248			`else`
249			`null;`
250	4	schelleg	`end if;`
251
252			`end if;`
253
254			`end process;`
255
256
257			`-- handling memcore signalling`
258			`memcore_sig_gen_uclkd : process (D_ADD, MIN_ADDR, MAX_ADDR)`
259			`begin`
260
261	2	schelleg	`if D_ADD = MIN_ADDR then`
262			`empty_memcore <= '1';`
263			`else`
264			`empty_memcore <= '0';`
265	4	schelleg	`end if;`
266
267	2	schelleg	`if D_ADD = MAX_ADDR then`
268			`full_memcore <= '1';`
269			`else`
270			`full_memcore <= '0';`
271	4	schelleg	`end if;`
272
273			`end process;`
274
275
276			`-----------------------------------------------------------`
277			`------------------- THE ACTUAL FIFOS ----------------------`
278			`-----------------------------------------------------------`
279
280			`datain_reg : fifo_reg`
281			`Generic map(`
282			`WIDTH => WIDTH`
283			`)`
284			`PORT MAP(`
285			`clk => clk,`
286			`din => din_datain,`
287			`rd_en => re_datain,`
288			`rst => Reset,`
289			`wr_en => we_datain,`
290			`dout => dout_datain,`
291			`empty => empty_datain,`
292			`full => full_datain`
293			`);`
294
295
296	2	schelleg	`memcore: dpmem`
297			`generic map (`
298			`ADD_WIDTH =>ADD_WIDTH,`
299			`WIDTH => WIDTH`
300			`)`
301			`port map (clk => clk,`
302			`reset => rst_n,`
303			`w_add => W_ADD,`
304			`r_add => R_ADD,`
305			`Data_in => din_memcore,`
306			`data_out => dout_memcore,`
307			`wr => we_memcore,`
308	4	schelleg	`re => re_memcore);`
309
310
311			`dataout_reg : fifo_reg`
312			`Generic map(`
313			`WIDTH => WIDTH`
314			`)`
315			`PORT MAP(`
316			`clk => clk,`
317			`din => din_dataout,`
318			`rd_en => re_dataout,`
319			`rst => reset,`
320			`wr_en => we_dataout,`
321			`dout => dout_dataout,`
322			`empty => empty_dataout,`
323			`full => full_dataout`
324			`);`
325
326
327
328
329			`end Behavioral;`