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[/] [pmodsf3driver/] [trunk/] [hw/] [simulations/] [Testbench_Top_PmodSF3Driver.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 ldalmasso
------------------------------------------------------------------------
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-- Engineer:    Dalmasso Loic
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-- Create Date: 11/03/2025
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-- Module Name: Top_PmodSF3Driver
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-- Description:
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--      Top Module including Pmod SF3 Driver for the 32 MB NOR Flash memory MT25QL256ABA.
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--
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-- Ports
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--              Input   -       i_sys_clock: System Input Clock
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--              Input   -       i_reset: Module Reset ('0': No Reset, '1': Reset)
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--              Input   -       i_start: Start Pmod SF3 Transmission ('0': No Start, '1': Start)
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--              Output  -       o_led: Pmod SF3 Data from Memory
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--              Output  -       o_reset: Pmod SF3 Reset ('0': Reset, '1': No Reset)
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--              Output  -       o_sclk: Pmod SF3SPI Serial Clock
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--              In/Out  -       io_dq: Pmod SF3SPI Data Lines (Simple, Dual or Quad Modes)
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--              Output  -       o_ss: Pmod SF3 SPI Slave Select Line ('0': Enable, '1': Disable)
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------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY Testbench_Top_PmodSF3Driver is
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END Testbench_Top_PmodSF3Driver;
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ARCHITECTURE Behavioral of Testbench_Top_PmodSF3Driver is
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COMPONENT Top_PmodSF3Driver is
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PORT(
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    i_sys_clock: IN STD_LOGIC;
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    i_reset: IN STD_LOGIC;
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    i_start: IN STD_LOGIC;
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    o_led: OUT UNSIGNED(15 downto 0);
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    -- PMode Ports
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    o_reset: OUT STD_LOGIC;
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    o_sclk: OUT STD_LOGIC;
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    io_dq: INOUT STD_LOGIC_VECTOR(3 downto 0);
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    o_ss: OUT STD_LOGIC
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);
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END COMPONENT;
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signal sys_clock: STD_LOGIC := '0';
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signal reset: STD_LOGIC := '0';
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signal start: STD_LOGIC := '0';
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signal led: UNSIGNED(15 downto 0) := (others => '0');
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signal reset_mem: STD_LOGIC := '0';
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signal sclk: STD_LOGIC := '0';
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signal dq: STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
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signal ss: STD_LOGIC := '1';
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begin
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-- Clock 100 MHz
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sys_clock <= not(sys_clock) after 5 ns;
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-- Reset
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reset <= '1', '0' after 4800 ns;
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-- Start
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start <= '0',
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        -- SPI Single Mode --
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        -- Read Volatile Dummy Cycles
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        '1' after 5000 ns, '0' after 5326 ns;
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-- SPI DQ[3:0]
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dq <=   (others => 'Z'),
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        -- SPI Single Mode --
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        -- Read Volatile Dummy Cycles
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        -- 1 Byte (0xFB)
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        "0010" after 5225 ns,
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        "0010" after 5245 ns,
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        "0010" after 5265 ns,
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        "0010" after 5285 ns,
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        "0010" after 5305 ns,
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        "0000" after 5325 ns,
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        "0010" after 5345 ns,
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        "0010" after 5365 ns,
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        (others => 'Z') after 5385 ns;
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uut: Top_PmodSF3Driver
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    PORT map(
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        i_sys_clock => sys_clock,
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        i_reset => reset,
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        i_start => start,
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        o_led => led,
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        o_reset => reset_mem,
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        o_sclk => sclk,
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        io_dq => dq,
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        o_ss => ss);
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end Behavioral;

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