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[/] [pmodsf3driver/] [trunk/] [hw/] [sources/] [PmodSF3SPIController.vhd] - Blame information for rev 2

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------------------------------------------------------------------------
-- Engineer:    Dalmasso Loic
-- Create Date: 19/02/2025
-- Module Name: PmodSF3SPIController
-- Description:
--      Pmod SF3 SPI Controller for the 32 MB NOR Flash Memory MT25QL256ABA.
--              Supports Single, Dual and Quad SPI Modes:
--              | i_spi_dual_enable | i_spi_single_enable | SPI Mode
--              |          0            |          1              | Single
--              |          1            |          1              | Single
--              |          1            |          0              | Dual
--              |          0            |          1              | Quad
--
--              The 'o_ready' signal indicates this module is ready to start new SPI transmission.
--              The 'i_start' signal starts the SPI communication, according to the mode (Read or Write memory), command/address/data bytes.
--              In Write operation, when the 'o_next_data_w' is set to '1', the MSB of the 'i_data_w' is loaded.
--              In Read operation, when the 'o_data_ready', data from memory is available in 'o_data_r' signal.
--
-- Ports
--              Input   -       i_sys_clock: System Input Clock
--              Input   -       i_sys_clock_en: System Input Clock Enable
--              Input   -       i_reset: System Input Reset ('0': No Reset, '1': Reset)
--              Input   -       i_start: Start SPI Transmission ('0': No Start, '1': Start)
--              Input   -       i_spi_single_enable: Enable SPI Single Mode ('0': Disable, '1': Enable)
--              Input   -       i_spi_dual_enable: Enable SPI Dual Mode ('0': Disable, '1': Enable)
--              Input   -       i_mode: Set Memory Operation Mode ('0': Write, '1': Mode)
--              Input   -       i_command: Command Byte
--              Input   -       i_addr_bytes: Number of Address Bytes to use (0 to 3 bytes)
--              Input   -       i_addr: Address Bytes
--              Input   -       i_dummy_cycles: Number of Dummy Cycles (0 to 14 cycles)
--              Input   -       i_data_bytes: Number of Data Bytes to write
--              Input   -       i_data_w: Data Bytes to write
--              Output  -       o_next_data_w: Next bit of Data Bytes trigger ('0': Disable, '1': Enable)
--              Output  -       o_data_r: Data Bytes read from Memory
--              Output  -       o_data_ready: Data Bytes read from Memory Ready ('0': NOT Ready, '1': Ready)
--              Output  -       o_ready: System Ready for transmission
--              Output  -       o_reset: Memory Reset ('0': Reset, '1': No Reset)
--              Output  -       o_sclk: SPI Serial Clock
--              In/Out  -       io_dq: SPI Serial Data
--              Output  -       o_ss: SPI Slave Select Line ('0': Enable, '1': Disable)
------------------------------------------------------------------------
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
 
ENTITY PmodSF3SPIController is
 
PORT(
        -- Module Control
        i_sys_clock: IN STD_LOGIC;
        i_sys_clock_en: IN STD_LOGIC;
        i_reset: IN STD_LOGIC;
        i_start: IN STD_LOGIC;
        -- SPI Mode Config (Single, Dual or Quad)
        i_spi_single_enable: IN STD_LOGIC;
        i_spi_dual_enable: IN STD_LOGIC;
        -- Memory Command/Addr/Data
        i_mode: IN STD_LOGIC;
        i_command: IN UNSIGNED(7 downto 0);
        i_addr_bytes: IN INTEGER range 0 to 3;
        i_addr: IN UNSIGNED(23 downto 0);
        i_dummy_cycles: IN INTEGER range 0 to 14;
        i_data_bytes: IN INTEGER;
        i_data_w: IN UNSIGNED(7 downto 0);
        o_next_data_w: OUT STD_LOGIC;
        o_data_r: OUT UNSIGNED(7 downto 0);
        o_data_ready: OUT STD_LOGIC;
        -- Module Outputs
        o_ready: OUT STD_LOGIC;
        o_reset: OUT STD_LOGIC;
        o_sclk: OUT STD_LOGIC;
        io_dq: INOUT STD_LOGIC_VECTOR(3 downto 0);
        o_ss: OUT STD_LOGIC
);
 
END PmodSF3SPIController;
 
ARCHITECTURE Behavioral of PmodSF3SPIController is
 
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
-- SPI Write Register Length: Command (1 Byte) + Address (3 Bytes) + Data (1 Byte)
constant SPI_WRITE_REGISTER_LENGTH: INTEGER := 40;
 
-- SPI Write Register Indexes
constant SPI_WRITE_REGISTER_CMD_MSB: INTEGER := SPI_WRITE_REGISTER_LENGTH-1;
constant SPI_WRITE_REGISTER_CMD_LSB: INTEGER := SPI_WRITE_REGISTER_LENGTH-8;
constant SPI_WRITE_REGISTER_ADDR_DATA_MSB: INTEGER := SPI_WRITE_REGISTER_LENGTH-9;
 
-- SPI Empty Write Bits
constant EMPTY_WRITE_BITS: UNSIGNED(SPI_WRITE_REGISTER_ADDR_DATA_MSB-8 downto 0) := (others => '0');
 
-- SPI SCLK IDLE Bit
constant SPI_SCLK_IDLE: STD_LOGIC := '1';
 
-- SPI DQ IDLE Bit
constant SPI_DQ_IDLE: STD_LOGIC := 'Z';
 
-- SPI Disable Slave Select Bit
constant DISABLE_SS_BIT: STD_LOGIC := '1';
 
-- SPI Bit Counter Increment
constant SPI_BIT_COUNTER_INCREMENT_1: UNSIGNED(2 downto 0) := "001";
constant SPI_BIT_COUNTER_INCREMENT_2: UNSIGNED(2 downto 0) := "010";
constant SPI_BIT_COUNTER_INCREMENT_4: UNSIGNED(2 downto 0) := "100";
 
-- SPI Bit Counter Ends
constant SPI_SINGLE_BIT_COUNTER_END: UNSIGNED(2 downto 0) := "111";
constant SPI_DUAL_BIT_COUNTER_END: UNSIGNED(2 downto 0) := "110";
constant SPI_QUAD_BIT_COUNTER_END: UNSIGNED(2 downto 0) := "100";
 
-- Memory Read Mode
constant MEM_READ_MODE: STD_LOGIC := '1';
constant MEM_WRITE_MODE: STD_LOGIC := '0';
 
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- SPI Controller States
TYPE spiState is (IDLE, WRITE_CMD, WRITE_ADDR, DUMMY_CYCLES, BYTES_TXRX, STOP_TX);
signal state: spiState := IDLE;
signal next_state: spiState;
 
-- SPI Modes
signal spi_single_enable_reg: STD_LOGIC := '0';
signal spi_dual_enable_reg: STD_LOGIC := '0';
 
-- Memory Operation Mode
signal mem_mode_reg: STD_LOGIC := '0';
 
-- Address & Data Byte Number
signal addr_bytes_reg: INTEGER range 0 to 3 := 0;
signal data_bytes_reg: INTEGER := 0;
 
-- Data to Memory
signal data_w_reg: UNSIGNED(SPI_WRITE_REGISTER_LENGTH-1 downto 0) := (others => '0');
 
-- Number of Dummy Cycles
signal dummy_cycles_reg: INTEGER range 0 to 14 := 0;
 
-- Data from Memory
signal data_r_reg: UNSIGNED(7 downto 0) := (others => '0');
signal data_r_ready_reg: STD_LOGIC := '0';
 
-- SPI Transmission Bit Counter
signal bit_counter: UNSIGNED(2 downto 0) := (others => '0');
signal bit_counter_increment: UNSIGNED(2 downto 0) := (others => '0');
signal bit_counter_end: STD_LOGIC := '0';
 
-- SPI SCLK
signal sclk_reg: STD_LOGIC := '0';
signal sclk_edge_reg0: STD_LOGIC := '0';
signal sclk_edge_reg1: STD_LOGIC := '0';
signal sclk_rising_edge: STD_LOGIC := '0';
signal sclk_falling_edge: STD_LOGIC := '0';
 
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
 
        -----------------------
        -- SPI State Machine --
        -----------------------
        -- SPI State
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Reset
                        if (i_reset = '1') then
                                state <= IDLE;
 
                        -- Clock Enable
                        elsif (i_sys_clock_en = '1') then
                                state <= next_state;
                        end if;
 
                end if;
        end process;
 
        -- SPI Next State
        process(state, i_start, bit_counter_end, mem_mode_reg, addr_bytes_reg, dummy_cycles_reg, data_bytes_reg)
        begin
                case state is
                        when IDLE =>    if (i_start = '1') then
                                                                next_state <= WRITE_CMD;
                                                        else
                                                                next_state <= IDLE;
                                                        end if;
 
                        -- Write Command Byte
                        when WRITE_CMD =>
                                                        -- End of Write Command Byte
                                                        if (bit_counter_end = '1') then
 
                                                                -- Address Bytes
                                                                if (addr_bytes_reg = 0) then
                                                                        next_state <= BYTES_TXRX;
                                                                else
                                                                        next_state <= WRITE_ADDR;
                                                                end if;
 
                                                        -- Continue Write Command Byte
                                                        else
                                                                next_state <= WRITE_CMD;
                                                        end if;
 
                        -- Write Address Bytes
                        when WRITE_ADDR =>
                                                        -- End of Write Address Bytes
                                                        if (bit_counter_end = '1') and (addr_bytes_reg <= 1) then
 
                                                                -- Dummy Cycles
                                                                if (mem_mode_reg = MEM_READ_MODE) and (dummy_cycles_reg /= 0) then
                                                                        next_state <= DUMMY_CYCLES;
                                                                else
                                                                        next_state <= BYTES_TXRX;
                                                                end if;
 
                                                        -- Continue Write Address Bytes
                                                        else
                                                                next_state <= WRITE_ADDR;
                                                        end if;
 
                        -- Dummy Cycles
                        when DUMMY_CYCLES =>
                                                        -- End of Dummy Cycles
                                                        if (dummy_cycles_reg = 0) then
                                                                next_state <= BYTES_TXRX;
 
                                                        -- Continue Waiting Dummy Cycles
                                                        else
                                                                next_state <= DUMMY_CYCLES;
                                                        end if;
 
                        -- Read/Write Data Bytes
                        when BYTES_TXRX =>
                                                        -- End of Write Data Byte
                                                        if (bit_counter_end = '1') and (data_bytes_reg <= 1) then
                                                                next_state <= STOP_TX;
                                                        else
                                                                next_state <= BYTES_TXRX;
                                                        end if;
 
                        -- End of Transmission
                        when others => next_state <= IDLE;
                end case;
        end process;
 
        ---------------------
        -- SPI SCLK Output --
        ---------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Reset SCLK
                                if (state = IDLE) or (state = STOP_TX) then
                                        sclk_reg <= SPI_SCLK_IDLE;
 
                                -- Generate SCLK
                                else
                                        sclk_reg <= not(sclk_reg);
                                end if;
 
                        end if;
                end if;
        end process;
        o_sclk <= sclk_reg;
 
        -----------------------------
        -- SPI SCLK Edge Detection --
        -----------------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- SCLK Edge Detection
                                sclk_edge_reg0 <= sclk_reg;
                                sclk_edge_reg1 <= sclk_edge_reg0;
                        end if;
                end if;
        end process;
        sclk_rising_edge <= sclk_edge_reg0 and not(sclk_edge_reg1);
        sclk_falling_edge <= not(sclk_edge_reg0) and sclk_edge_reg1;
 
        ----------------------
        -- SPI Mode Handler --
        ----------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Load SPI Mode Inputs
                                if (state = IDLE) then
                                        spi_single_enable_reg <= i_spi_single_enable;
                                        spi_dual_enable_reg <= i_spi_dual_enable;
                                end if;
                        end if;
                end if;
        end process;
 
        -------------------------
        -- Memory Mode Handler --
        -------------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Load Memory Mode Input
                                if (state = IDLE) then
                                        mem_mode_reg <= i_mode;
                                end if;
                        end if;
                end if;
        end process;
 
        -------------------------------------
        -- Command, Address & Data Handler --
        -------------------------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Load Inputs
                                if (state = IDLE) then
 
                                        -- Command Byte
                                        data_w_reg(SPI_WRITE_REGISTER_CMD_MSB downto SPI_WRITE_REGISTER_CMD_LSB) <= i_command;
 
                                        -- Address & Data Bytes
                                        if (i_addr_bytes /= 0) then
                                                data_w_reg(SPI_WRITE_REGISTER_ADDR_DATA_MSB downto 0) <= i_addr & i_data_w;
 
                                        -- Data Byte only
                                        else
                                                data_w_reg(SPI_WRITE_REGISTER_ADDR_DATA_MSB downto 0) <= i_data_w & EMPTY_WRITE_BITS;
                                        end if;
 
                                -- Handle Next Data to Write on SCLK Falling Edge (Left-Shift Data Write Register & new Data Input)
                                elsif (sclk_falling_edge = '1') then
 
                                        -- Write Command, Address and Data (in Write Mode only)
                                        if (state = WRITE_CMD) or ((state = WRITE_ADDR) and (addr_bytes_reg /= 0)) or ((state = BYTES_TXRX) and (data_bytes_reg /= 0) and (mem_mode_reg = MEM_WRITE_MODE)) then
 
                                                -- Single SPI Mode: DQ0
                                                if (spi_single_enable_reg = '1') then
                                                        data_w_reg <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-2 downto 0) & i_data_w(7);
 
                                                -- Dual SPI Mode: DQ[1:0]
                                                elsif (spi_dual_enable_reg = '1') then
                                                        data_w_reg <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-3 downto 0) & i_data_w(7 downto 6);
 
                                                -- Quad SPI Mode: DQ[3:0]
                                                else
                                                        data_w_reg <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-5 downto 0) & i_data_w(7 downto 4);
                                                end if;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        -----------------------------
        -- Next Write Data Trigger --
        -----------------------------
        o_next_data_w <= '1' when (mem_mode_reg = MEM_WRITE_MODE) and (sclk_falling_edge = '1') and ((state = WRITE_CMD) or (state = WRITE_ADDR) or (state = BYTES_TXRX)) else '0';
 
        ---------------------------
        -- Address Bytes Handler --
        ----------------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Load Address Bytes Input
                                if (state = IDLE) then
                                        addr_bytes_reg <= i_addr_bytes;
 
                                -- Address Bytes State
                                elsif (state = WRITE_ADDR) and (bit_counter_end = '1') then
                                        -- Decrement Address Bytes
                                        addr_bytes_reg <= addr_bytes_reg -1;
                                end if;
                        end if;
                end if;
        end process;
 
        --------------------------
        -- Dummy Cycles Handler --
        --------------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Load Dummy Cycles Input
                                if (state = IDLE) then
                                        dummy_cycles_reg <= i_dummy_cycles;
 
                                -- Dummy Cycles State (only at SCLK Rising Edge)
                                elsif (state = DUMMY_CYCLES) and (sclk_rising_edge = '1') then
                                        -- Decrement Dummy Cycles
                                        dummy_cycles_reg <= dummy_cycles_reg -1;
                                end if;
                        end if;
                end if;
        end process;
 
        ------------------------
        -- Data Bytes Handler --
        ------------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Load Data Bytes Input
                                if (state = IDLE) then
                                        data_bytes_reg <= i_data_bytes;
 
                                -- Data Bytes State
                                elsif (state = BYTES_TXRX) and (bit_counter_end = '1') then
                                        -- Decrement Data Bytes
                                        data_bytes_reg <= data_bytes_reg -1;
                                end if;
                        end if;
                end if;
        end process;
 
        ---------------------
        -- SPI Bit Counter --
        ---------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Bit Counter Increment
                                if (state = IDLE) then
 
                                        -- Single SPI Mode
                                        if (spi_single_enable_reg = '1') then
                                                bit_counter_increment <= SPI_BIT_COUNTER_INCREMENT_1;
 
                                        -- Dual SPI Mode
                                        elsif (spi_dual_enable_reg = '1') then
                                                bit_counter_increment <= SPI_BIT_COUNTER_INCREMENT_2;
 
                                        -- Quad SPI Mode
                                        else
                                                bit_counter_increment <= SPI_BIT_COUNTER_INCREMENT_4;
                                        end if;
                                end if;
 
                                -- Reset Bit Counter
                                if (state = IDLE) or (state = DUMMY_CYCLES) then
                                        bit_counter <= (others => '0');
 
                                -- Increment Bit Counter (only at SCLK Falling Edge)
                                elsif (sclk_falling_edge = '1') then
                                        bit_counter <= bit_counter +bit_counter_increment;
                                end if;
                        end if;
                end if;
        end process;
 
        -- Bit Counter End
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Bit Counter End Trigger (only at SCLK Rising Edge)
                                if (sclk_rising_edge = '1') then
 
                                        -- Single SPI Mode
                                        if (spi_single_enable_reg = '1') and (bit_counter = SPI_SINGLE_BIT_COUNTER_END) then
                                                bit_counter_end <= '1';
 
                                        -- Dual SPI Mode
                                        elsif (spi_dual_enable_reg = '1') and (bit_counter = SPI_DUAL_BIT_COUNTER_END) then
                                                bit_counter_end <= '1';
 
                                        -- Quad SPI Mode
                                        elsif (spi_single_enable_reg = '0') and (spi_dual_enable_reg = '0') and (bit_counter = SPI_QUAD_BIT_COUNTER_END) then
                                                bit_counter_end <= '1';
                                        end if;
 
                                -- Reset Bit Counter End
                                else
                                        bit_counter_end <= '0';
                                end if;
                        end if;
                end if;
        end process;
 
        ---------------------------
        -- SPI Write Data (MOSI) --
        ---------------------------
        process(state, mem_mode_reg, spi_single_enable_reg, spi_dual_enable_reg, data_w_reg)
        begin
                if (state = WRITE_CMD) or (state = WRITE_ADDR) or ((state = BYTES_TXRX) and (mem_mode_reg = MEM_WRITE_MODE)) then
 
                        -- Single SPI Mode: DQ0
                        if (spi_single_enable_reg = '1') then
                                io_dq(3) <= SPI_DQ_IDLE;
                                io_dq(2) <= SPI_DQ_IDLE;
                                io_dq(1) <= SPI_DQ_IDLE;
                                io_dq(0) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-1);
 
                        -- Dual SPI Mode: DQ[1:0]
                        elsif (spi_dual_enable_reg = '1') then
                                io_dq(3) <= SPI_DQ_IDLE;
                                io_dq(2) <= SPI_DQ_IDLE;
                                io_dq(1) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-1);
                                io_dq(0) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-2);
 
                        -- Quad SPI Mode: DQ[3:0]
                        else
                                io_dq(3) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-1);
                                io_dq(2) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-2);
                                io_dq(1) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-3);
                                io_dq(0) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-4);
                        end if;
 
                -- IDLE
                else
                        io_dq <= (others => SPI_DQ_IDLE);
                end if;
        end process;
 
        --------------------------
        -- SPI Read Data (MISO) --
        --------------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Sampling Read Data Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Next Data to Write on SCLK Rising Edge 
                                if (sclk_rising_edge = '1') and (mem_mode_reg = MEM_READ_MODE) and (state = BYTES_TXRX) then
 
                                        -- Check Last Byte Cycle                                        
                                        if (data_bytes_reg /= 1) or (bit_counter_end = '0') then
 
                                                -- Single SPI Mode: DQ1
                                                if (spi_single_enable_reg = '1') then
                                                        data_r_reg(7 downto 1) <= data_r_reg(6 downto 0);
                                                        data_r_reg(0) <= io_dq(1);
 
                                                -- Dual SPI Mode: DQ[1:0]
                                                elsif (spi_dual_enable_reg = '1')  then
                                                        data_r_reg(7 downto 2) <= data_r_reg(5 downto 0);
                                                        data_r_reg(1) <= io_dq(1);
                                                        data_r_reg(0) <= io_dq(0);
 
                                                -- Quad SPI Mode: DQ[3:0]
                                                else
                                                        data_r_reg(7 downto 4) <= data_r_reg(3 downto 0);
                                                        data_r_reg(3) <= io_dq(3);
                                                        data_r_reg(2) <= io_dq(2);
                                                        data_r_reg(1) <= io_dq(1);
                                                        data_r_reg(0) <= io_dq(0);
                                                end if;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
        o_data_r <= data_r_reg;
 
        -------------------------
        -- SPI Read Data Valid --
        -------------------------
        process(i_sys_clock)
        begin
                if rising_edge(i_sys_clock) then
 
                        -- Clock Enable
                        if (i_sys_clock_en = '1') then
 
                                -- Data Read Ready
                                if (mem_mode_reg = MEM_READ_MODE) and (state = BYTES_TXRX) and (bit_counter_end = '1') then
                                        data_r_ready_reg <= '1';
 
                                -- Data Read NOT Ready
                                else
                                        data_r_ready_reg <= '0';
                                end if;
                        end if;
                end if;
        end process;
        o_data_ready <= data_r_ready_reg;
 
        ----------------------
        -- SPI Ready Status --
        ----------------------
        o_ready <= '1' when state = IDLE else '0';
 
        ------------------
        -- Reset Output --
        ------------------
        o_reset <= not(i_reset);
 
        ---------------------------
        -- SPI Slave Select Line --
        ---------------------------
        o_ss <= DISABLE_SS_BIT when (state = IDLE) or (state = STOP_TX) else not(DISABLE_SS_BIT);
 
end Behavioral;

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[/] [pmodsf3driver/] [trunk/] [hw/] [sources/] [PmodSF3SPIController.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ldalmasso	`------------------------------------------------------------------------`
2			`-- Engineer: Dalmasso Loic`
3			`-- Create Date: 19/02/2025`
4			`-- Module Name: PmodSF3SPIController`
5			`-- Description:`
6			`-- Pmod SF3 SPI Controller for the 32 MB NOR Flash Memory MT25QL256ABA.`
7			`-- Supports Single, Dual and Quad SPI Modes:`
8			`-- \| i_spi_dual_enable \| i_spi_single_enable \| SPI Mode`
9			`-- \| 0 \| 1 \| Single`
10			`-- \| 1 \| 1 \| Single`
11			`-- \| 1 \| 0 \| Dual`
12			`-- \| 0 \| 1 \| Quad`
13			`--`
14			`-- The 'o_ready' signal indicates this module is ready to start new SPI transmission.`
15			`-- The 'i_start' signal starts the SPI communication, according to the mode (Read or Write memory), command/address/data bytes.`
16			`-- In Write operation, when the 'o_next_data_w' is set to '1', the MSB of the 'i_data_w' is loaded.`
17			`-- In Read operation, when the 'o_data_ready', data from memory is available in 'o_data_r' signal.`
18			`--`
19			`-- Ports`
20			`-- Input - i_sys_clock: System Input Clock`
21			`-- Input - i_sys_clock_en: System Input Clock Enable`
22			`-- Input - i_reset: System Input Reset ('0': No Reset, '1': Reset)`
23			`-- Input - i_start: Start SPI Transmission ('0': No Start, '1': Start)`
24			`-- Input - i_spi_single_enable: Enable SPI Single Mode ('0': Disable, '1': Enable)`
25			`-- Input - i_spi_dual_enable: Enable SPI Dual Mode ('0': Disable, '1': Enable)`
26			`-- Input - i_mode: Set Memory Operation Mode ('0': Write, '1': Mode)`
27			`-- Input - i_command: Command Byte`
28			`-- Input - i_addr_bytes: Number of Address Bytes to use (0 to 3 bytes)`
29			`-- Input - i_addr: Address Bytes`
30			`-- Input - i_dummy_cycles: Number of Dummy Cycles (0 to 14 cycles)`
31			`-- Input - i_data_bytes: Number of Data Bytes to write`
32			`-- Input - i_data_w: Data Bytes to write`
33			`-- Output - o_next_data_w: Next bit of Data Bytes trigger ('0': Disable, '1': Enable)`
34			`-- Output - o_data_r: Data Bytes read from Memory`
35			`-- Output - o_data_ready: Data Bytes read from Memory Ready ('0': NOT Ready, '1': Ready)`
36			`-- Output - o_ready: System Ready for transmission`
37			`-- Output - o_reset: Memory Reset ('0': Reset, '1': No Reset)`
38			`-- Output - o_sclk: SPI Serial Clock`
39			`-- In/Out - io_dq: SPI Serial Data`
40			`-- Output - o_ss: SPI Slave Select Line ('0': Enable, '1': Disable)`
41			`------------------------------------------------------------------------`
42
43			`LIBRARY IEEE;`
44			`USE IEEE.STD_LOGIC_1164.ALL;`
45			`USE IEEE.NUMERIC_STD.ALL;`
46
47			`ENTITY PmodSF3SPIController is`
48
49			`PORT(`
50			`-- Module Control`
51			`i_sys_clock: IN STD_LOGIC;`
52			`i_sys_clock_en: IN STD_LOGIC;`
53			`i_reset: IN STD_LOGIC;`
54			`i_start: IN STD_LOGIC;`
55			`-- SPI Mode Config (Single, Dual or Quad)`
56			`i_spi_single_enable: IN STD_LOGIC;`
57			`i_spi_dual_enable: IN STD_LOGIC;`
58			`-- Memory Command/Addr/Data`
59			`i_mode: IN STD_LOGIC;`
60			`i_command: IN UNSIGNED(7 downto 0);`
61			`i_addr_bytes: IN INTEGER range 0 to 3;`
62			`i_addr: IN UNSIGNED(23 downto 0);`
63			`i_dummy_cycles: IN INTEGER range 0 to 14;`
64			`i_data_bytes: IN INTEGER;`
65			`i_data_w: IN UNSIGNED(7 downto 0);`
66			`o_next_data_w: OUT STD_LOGIC;`
67			`o_data_r: OUT UNSIGNED(7 downto 0);`
68			`o_data_ready: OUT STD_LOGIC;`
69			`-- Module Outputs`
70			`o_ready: OUT STD_LOGIC;`
71			`o_reset: OUT STD_LOGIC;`
72			`o_sclk: OUT STD_LOGIC;`
73			`io_dq: INOUT STD_LOGIC_VECTOR(3 downto 0);`
74			`o_ss: OUT STD_LOGIC`
75			`);`
76
77			`END PmodSF3SPIController;`
78
79			`ARCHITECTURE Behavioral of PmodSF3SPIController is`
80
81			`------------------------------------------------------------------------`
82			`-- Constant Declarations`
83			`------------------------------------------------------------------------`
84			`-- SPI Write Register Length: Command (1 Byte) + Address (3 Bytes) + Data (1 Byte)`
85			`constant SPI_WRITE_REGISTER_LENGTH: INTEGER := 40;`
86
87			`-- SPI Write Register Indexes`
88			`constant SPI_WRITE_REGISTER_CMD_MSB: INTEGER := SPI_WRITE_REGISTER_LENGTH-1;`
89			`constant SPI_WRITE_REGISTER_CMD_LSB: INTEGER := SPI_WRITE_REGISTER_LENGTH-8;`
90			`constant SPI_WRITE_REGISTER_ADDR_DATA_MSB: INTEGER := SPI_WRITE_REGISTER_LENGTH-9;`
91
92			`-- SPI Empty Write Bits`
93			`constant EMPTY_WRITE_BITS: UNSIGNED(SPI_WRITE_REGISTER_ADDR_DATA_MSB-8 downto 0) := (others => '0');`
94
95			`-- SPI SCLK IDLE Bit`
96			`constant SPI_SCLK_IDLE: STD_LOGIC := '1';`
97
98			`-- SPI DQ IDLE Bit`
99			`constant SPI_DQ_IDLE: STD_LOGIC := 'Z';`
100
101			`-- SPI Disable Slave Select Bit`
102			`constant DISABLE_SS_BIT: STD_LOGIC := '1';`
103
104			`-- SPI Bit Counter Increment`
105			`constant SPI_BIT_COUNTER_INCREMENT_1: UNSIGNED(2 downto 0) := "001";`
106			`constant SPI_BIT_COUNTER_INCREMENT_2: UNSIGNED(2 downto 0) := "010";`
107			`constant SPI_BIT_COUNTER_INCREMENT_4: UNSIGNED(2 downto 0) := "100";`
108
109			`-- SPI Bit Counter Ends`
110			`constant SPI_SINGLE_BIT_COUNTER_END: UNSIGNED(2 downto 0) := "111";`
111			`constant SPI_DUAL_BIT_COUNTER_END: UNSIGNED(2 downto 0) := "110";`
112			`constant SPI_QUAD_BIT_COUNTER_END: UNSIGNED(2 downto 0) := "100";`
113
114			`-- Memory Read Mode`
115			`constant MEM_READ_MODE: STD_LOGIC := '1';`
116			`constant MEM_WRITE_MODE: STD_LOGIC := '0';`
117
118			`------------------------------------------------------------------------`
119			`-- Signal Declarations`
120			`------------------------------------------------------------------------`
121			`-- SPI Controller States`
122			`TYPE spiState is (IDLE, WRITE_CMD, WRITE_ADDR, DUMMY_CYCLES, BYTES_TXRX, STOP_TX);`
123			`signal state: spiState := IDLE;`
124			`signal next_state: spiState;`
125
126			`-- SPI Modes`
127			`signal spi_single_enable_reg: STD_LOGIC := '0';`
128			`signal spi_dual_enable_reg: STD_LOGIC := '0';`
129
130			`-- Memory Operation Mode`
131			`signal mem_mode_reg: STD_LOGIC := '0';`
132
133			`-- Address & Data Byte Number`
134			`signal addr_bytes_reg: INTEGER range 0 to 3 := 0;`
135			`signal data_bytes_reg: INTEGER := 0;`
136
137			`-- Data to Memory`
138			`signal data_w_reg: UNSIGNED(SPI_WRITE_REGISTER_LENGTH-1 downto 0) := (others => '0');`
139
140			`-- Number of Dummy Cycles`
141			`signal dummy_cycles_reg: INTEGER range 0 to 14 := 0;`
142
143			`-- Data from Memory`
144			`signal data_r_reg: UNSIGNED(7 downto 0) := (others => '0');`
145			`signal data_r_ready_reg: STD_LOGIC := '0';`
146
147			`-- SPI Transmission Bit Counter`
148			`signal bit_counter: UNSIGNED(2 downto 0) := (others => '0');`
149			`signal bit_counter_increment: UNSIGNED(2 downto 0) := (others => '0');`
150			`signal bit_counter_end: STD_LOGIC := '0';`
151
152			`-- SPI SCLK`
153			`signal sclk_reg: STD_LOGIC := '0';`
154			`signal sclk_edge_reg0: STD_LOGIC := '0';`
155			`signal sclk_edge_reg1: STD_LOGIC := '0';`
156			`signal sclk_rising_edge: STD_LOGIC := '0';`
157			`signal sclk_falling_edge: STD_LOGIC := '0';`
158
159			`------------------------------------------------------------------------`
160			`-- Module Implementation`
161			`------------------------------------------------------------------------`
162			`begin`
163
164			`-----------------------`
165			`-- SPI State Machine --`
166			`-----------------------`
167			`-- SPI State`
168			`process(i_sys_clock)`
169			`begin`
170			`if rising_edge(i_sys_clock) then`
171
172			`-- Reset`
173			`if (i_reset = '1') then`
174			`state <= IDLE;`
175
176			`-- Clock Enable`
177			`elsif (i_sys_clock_en = '1') then`
178			`state <= next_state;`
179			`end if;`
180
181			`end if;`
182			`end process;`
183
184			`-- SPI Next State`
185			`process(state, i_start, bit_counter_end, mem_mode_reg, addr_bytes_reg, dummy_cycles_reg, data_bytes_reg)`
186			`begin`
187			`case state is`
188			`when IDLE => if (i_start = '1') then`
189			`next_state <= WRITE_CMD;`
190			`else`
191			`next_state <= IDLE;`
192			`end if;`
193
194			`-- Write Command Byte`
195			`when WRITE_CMD =>`
196			`-- End of Write Command Byte`
197			`if (bit_counter_end = '1') then`
198
199			`-- Address Bytes`
200			`if (addr_bytes_reg = 0) then`
201			`next_state <= BYTES_TXRX;`
202			`else`
203			`next_state <= WRITE_ADDR;`
204			`end if;`
205
206			`-- Continue Write Command Byte`
207			`else`
208			`next_state <= WRITE_CMD;`
209			`end if;`
210
211			`-- Write Address Bytes`
212			`when WRITE_ADDR =>`
213			`-- End of Write Address Bytes`
214			`if (bit_counter_end = '1') and (addr_bytes_reg <= 1) then`
215
216			`-- Dummy Cycles`
217			`if (mem_mode_reg = MEM_READ_MODE) and (dummy_cycles_reg /= 0) then`
218			`next_state <= DUMMY_CYCLES;`
219			`else`
220			`next_state <= BYTES_TXRX;`
221			`end if;`
222
223			`-- Continue Write Address Bytes`
224			`else`
225			`next_state <= WRITE_ADDR;`
226			`end if;`
227
228			`-- Dummy Cycles`
229			`when DUMMY_CYCLES =>`
230			`-- End of Dummy Cycles`
231			`if (dummy_cycles_reg = 0) then`
232			`next_state <= BYTES_TXRX;`
233
234			`-- Continue Waiting Dummy Cycles`
235			`else`
236			`next_state <= DUMMY_CYCLES;`
237			`end if;`
238
239			`-- Read/Write Data Bytes`
240			`when BYTES_TXRX =>`
241			`-- End of Write Data Byte`
242			`if (bit_counter_end = '1') and (data_bytes_reg <= 1) then`
243			`next_state <= STOP_TX;`
244			`else`
245			`next_state <= BYTES_TXRX;`
246			`end if;`
247
248			`-- End of Transmission`
249			`when others => next_state <= IDLE;`
250			`end case;`
251			`end process;`
252
253			`---------------------`
254			`-- SPI SCLK Output --`
255			`---------------------`
256			`process(i_sys_clock)`
257			`begin`
258			`if rising_edge(i_sys_clock) then`
259
260			`-- Clock Enable`
261			`if (i_sys_clock_en = '1') then`
262
263			`-- Reset SCLK`
264			`if (state = IDLE) or (state = STOP_TX) then`
265			`sclk_reg <= SPI_SCLK_IDLE;`
266
267			`-- Generate SCLK`
268			`else`
269			`sclk_reg <= not(sclk_reg);`
270			`end if;`
271
272			`end if;`
273			`end if;`
274			`end process;`
275			`o_sclk <= sclk_reg;`
276
277			`-----------------------------`
278			`-- SPI SCLK Edge Detection --`
279			`-----------------------------`
280			`process(i_sys_clock)`
281			`begin`
282			`if rising_edge(i_sys_clock) then`
283
284			`-- Clock Enable`
285			`if (i_sys_clock_en = '1') then`
286
287			`-- SCLK Edge Detection`
288			`sclk_edge_reg0 <= sclk_reg;`
289			`sclk_edge_reg1 <= sclk_edge_reg0;`
290			`end if;`
291			`end if;`
292			`end process;`
293			`sclk_rising_edge <= sclk_edge_reg0 and not(sclk_edge_reg1);`
294			`sclk_falling_edge <= not(sclk_edge_reg0) and sclk_edge_reg1;`
295
296			`----------------------`
297			`-- SPI Mode Handler --`
298			`----------------------`
299			`process(i_sys_clock)`
300			`begin`
301			`if rising_edge(i_sys_clock) then`
302
303			`-- Clock Enable`
304			`if (i_sys_clock_en = '1') then`
305
306			`-- Load SPI Mode Inputs`
307			`if (state = IDLE) then`
308			`spi_single_enable_reg <= i_spi_single_enable;`
309			`spi_dual_enable_reg <= i_spi_dual_enable;`
310			`end if;`
311			`end if;`
312			`end if;`
313			`end process;`
314
315			`-------------------------`
316			`-- Memory Mode Handler --`
317			`-------------------------`
318			`process(i_sys_clock)`
319			`begin`
320			`if rising_edge(i_sys_clock) then`
321
322			`-- Clock Enable`
323			`if (i_sys_clock_en = '1') then`
324
325			`-- Load Memory Mode Input`
326			`if (state = IDLE) then`
327			`mem_mode_reg <= i_mode;`
328			`end if;`
329			`end if;`
330			`end if;`
331			`end process;`
332
333			`-------------------------------------`
334			`-- Command, Address & Data Handler --`
335			`-------------------------------------`
336			`process(i_sys_clock)`
337			`begin`
338			`if rising_edge(i_sys_clock) then`
339
340			`-- Clock Enable`
341			`if (i_sys_clock_en = '1') then`
342
343			`-- Load Inputs`
344			`if (state = IDLE) then`
345
346			`-- Command Byte`
347			`data_w_reg(SPI_WRITE_REGISTER_CMD_MSB downto SPI_WRITE_REGISTER_CMD_LSB) <= i_command;`
348
349			`-- Address & Data Bytes`
350			`if (i_addr_bytes /= 0) then`
351			`data_w_reg(SPI_WRITE_REGISTER_ADDR_DATA_MSB downto 0) <= i_addr & i_data_w;`
352
353			`-- Data Byte only`
354			`else`
355			`data_w_reg(SPI_WRITE_REGISTER_ADDR_DATA_MSB downto 0) <= i_data_w & EMPTY_WRITE_BITS;`
356			`end if;`
357
358			`-- Handle Next Data to Write on SCLK Falling Edge (Left-Shift Data Write Register & new Data Input)`
359			`elsif (sclk_falling_edge = '1') then`
360
361			`-- Write Command, Address and Data (in Write Mode only)`
362			`if (state = WRITE_CMD) or ((state = WRITE_ADDR) and (addr_bytes_reg /= 0)) or ((state = BYTES_TXRX) and (data_bytes_reg /= 0) and (mem_mode_reg = MEM_WRITE_MODE)) then`
363
364			`-- Single SPI Mode: DQ0`
365			`if (spi_single_enable_reg = '1') then`
366			`data_w_reg <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-2 downto 0) & i_data_w(7);`
367
368			`-- Dual SPI Mode: DQ[1:0]`
369			`elsif (spi_dual_enable_reg = '1') then`
370			`data_w_reg <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-3 downto 0) & i_data_w(7 downto 6);`
371
372			`-- Quad SPI Mode: DQ[3:0]`
373			`else`
374			`data_w_reg <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-5 downto 0) & i_data_w(7 downto 4);`
375			`end if;`
376			`end if;`
377			`end if;`
378			`end if;`
379			`end if;`
380			`end process;`
381
382			`-----------------------------`
383			`-- Next Write Data Trigger --`
384			`-----------------------------`
385			`o_next_data_w <= '1' when (mem_mode_reg = MEM_WRITE_MODE) and (sclk_falling_edge = '1') and ((state = WRITE_CMD) or (state = WRITE_ADDR) or (state = BYTES_TXRX)) else '0';`
386
387			`---------------------------`
388			`-- Address Bytes Handler --`
389			`----------------------------`
390			`process(i_sys_clock)`
391			`begin`
392			`if rising_edge(i_sys_clock) then`
393
394			`-- Clock Enable`
395			`if (i_sys_clock_en = '1') then`
396
397			`-- Load Address Bytes Input`
398			`if (state = IDLE) then`
399			`addr_bytes_reg <= i_addr_bytes;`
400
401			`-- Address Bytes State`
402			`elsif (state = WRITE_ADDR) and (bit_counter_end = '1') then`
403			`-- Decrement Address Bytes`
404			`addr_bytes_reg <= addr_bytes_reg -1;`
405			`end if;`
406			`end if;`
407			`end if;`
408			`end process;`
409
410			`--------------------------`
411			`-- Dummy Cycles Handler --`
412			`--------------------------`
413			`process(i_sys_clock)`
414			`begin`
415			`if rising_edge(i_sys_clock) then`
416
417			`-- Clock Enable`
418			`if (i_sys_clock_en = '1') then`
419
420			`-- Load Dummy Cycles Input`
421			`if (state = IDLE) then`
422			`dummy_cycles_reg <= i_dummy_cycles;`
423
424			`-- Dummy Cycles State (only at SCLK Rising Edge)`
425			`elsif (state = DUMMY_CYCLES) and (sclk_rising_edge = '1') then`
426			`-- Decrement Dummy Cycles`
427			`dummy_cycles_reg <= dummy_cycles_reg -1;`
428			`end if;`
429			`end if;`
430			`end if;`
431			`end process;`
432
433			`------------------------`
434			`-- Data Bytes Handler --`
435			`------------------------`
436			`process(i_sys_clock)`
437			`begin`
438			`if rising_edge(i_sys_clock) then`
439
440			`-- Clock Enable`
441			`if (i_sys_clock_en = '1') then`
442
443			`-- Load Data Bytes Input`
444			`if (state = IDLE) then`
445			`data_bytes_reg <= i_data_bytes;`
446
447			`-- Data Bytes State`
448			`elsif (state = BYTES_TXRX) and (bit_counter_end = '1') then`
449			`-- Decrement Data Bytes`
450			`data_bytes_reg <= data_bytes_reg -1;`
451			`end if;`
452			`end if;`
453			`end if;`
454			`end process;`
455
456			`---------------------`
457			`-- SPI Bit Counter --`
458			`---------------------`
459			`process(i_sys_clock)`
460			`begin`
461			`if rising_edge(i_sys_clock) then`
462
463			`-- Clock Enable`
464			`if (i_sys_clock_en = '1') then`
465
466			`-- Bit Counter Increment`
467			`if (state = IDLE) then`
468
469			`-- Single SPI Mode`
470			`if (spi_single_enable_reg = '1') then`
471			`bit_counter_increment <= SPI_BIT_COUNTER_INCREMENT_1;`
472
473			`-- Dual SPI Mode`
474			`elsif (spi_dual_enable_reg = '1') then`
475			`bit_counter_increment <= SPI_BIT_COUNTER_INCREMENT_2;`
476
477			`-- Quad SPI Mode`
478			`else`
479			`bit_counter_increment <= SPI_BIT_COUNTER_INCREMENT_4;`
480			`end if;`
481			`end if;`
482
483			`-- Reset Bit Counter`
484			`if (state = IDLE) or (state = DUMMY_CYCLES) then`
485			`bit_counter <= (others => '0');`
486
487			`-- Increment Bit Counter (only at SCLK Falling Edge)`
488			`elsif (sclk_falling_edge = '1') then`
489			`bit_counter <= bit_counter +bit_counter_increment;`
490			`end if;`
491			`end if;`
492			`end if;`
493			`end process;`
494
495			`-- Bit Counter End`
496			`process(i_sys_clock)`
497			`begin`
498			`if rising_edge(i_sys_clock) then`
499
500			`-- Clock Enable`
501			`if (i_sys_clock_en = '1') then`
502
503			`-- Bit Counter End Trigger (only at SCLK Rising Edge)`
504			`if (sclk_rising_edge = '1') then`
505
506			`-- Single SPI Mode`
507			`if (spi_single_enable_reg = '1') and (bit_counter = SPI_SINGLE_BIT_COUNTER_END) then`
508			`bit_counter_end <= '1';`
509
510			`-- Dual SPI Mode`
511			`elsif (spi_dual_enable_reg = '1') and (bit_counter = SPI_DUAL_BIT_COUNTER_END) then`
512			`bit_counter_end <= '1';`
513
514			`-- Quad SPI Mode`
515			`elsif (spi_single_enable_reg = '0') and (spi_dual_enable_reg = '0') and (bit_counter = SPI_QUAD_BIT_COUNTER_END) then`
516			`bit_counter_end <= '1';`
517			`end if;`
518
519			`-- Reset Bit Counter End`
520			`else`
521			`bit_counter_end <= '0';`
522			`end if;`
523			`end if;`
524			`end if;`
525			`end process;`
526
527			`---------------------------`
528			`-- SPI Write Data (MOSI) --`
529			`---------------------------`
530			`process(state, mem_mode_reg, spi_single_enable_reg, spi_dual_enable_reg, data_w_reg)`
531			`begin`
532			`if (state = WRITE_CMD) or (state = WRITE_ADDR) or ((state = BYTES_TXRX) and (mem_mode_reg = MEM_WRITE_MODE)) then`
533
534			`-- Single SPI Mode: DQ0`
535			`if (spi_single_enable_reg = '1') then`
536			`io_dq(3) <= SPI_DQ_IDLE;`
537			`io_dq(2) <= SPI_DQ_IDLE;`
538			`io_dq(1) <= SPI_DQ_IDLE;`
539			`io_dq(0) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-1);`
540
541			`-- Dual SPI Mode: DQ[1:0]`
542			`elsif (spi_dual_enable_reg = '1') then`
543			`io_dq(3) <= SPI_DQ_IDLE;`
544			`io_dq(2) <= SPI_DQ_IDLE;`
545			`io_dq(1) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-1);`
546			`io_dq(0) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-2);`
547
548			`-- Quad SPI Mode: DQ[3:0]`
549			`else`
550			`io_dq(3) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-1);`
551			`io_dq(2) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-2);`
552			`io_dq(1) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-3);`
553			`io_dq(0) <= data_w_reg(SPI_WRITE_REGISTER_LENGTH-4);`
554			`end if;`
555
556			`-- IDLE`
557			`else`
558			`io_dq <= (others => SPI_DQ_IDLE);`
559			`end if;`
560			`end process;`
561
562			`--------------------------`
563			`-- SPI Read Data (MISO) --`
564			`--------------------------`
565			`process(i_sys_clock)`
566			`begin`
567			`if rising_edge(i_sys_clock) then`
568
569			`-- Sampling Read Data Enable`
570			`if (i_sys_clock_en = '1') then`
571
572			`-- Next Data to Write on SCLK Rising Edge`
573			`if (sclk_rising_edge = '1') and (mem_mode_reg = MEM_READ_MODE) and (state = BYTES_TXRX) then`
574
575			`-- Check Last Byte Cycle`
576			`if (data_bytes_reg /= 1) or (bit_counter_end = '0') then`
577
578			`-- Single SPI Mode: DQ1`
579			`if (spi_single_enable_reg = '1') then`
580			`data_r_reg(7 downto 1) <= data_r_reg(6 downto 0);`
581			`data_r_reg(0) <= io_dq(1);`
582
583			`-- Dual SPI Mode: DQ[1:0]`
584			`elsif (spi_dual_enable_reg = '1') then`
585			`data_r_reg(7 downto 2) <= data_r_reg(5 downto 0);`
586			`data_r_reg(1) <= io_dq(1);`
587			`data_r_reg(0) <= io_dq(0);`
588
589			`-- Quad SPI Mode: DQ[3:0]`
590			`else`
591			`data_r_reg(7 downto 4) <= data_r_reg(3 downto 0);`
592			`data_r_reg(3) <= io_dq(3);`
593			`data_r_reg(2) <= io_dq(2);`
594			`data_r_reg(1) <= io_dq(1);`
595			`data_r_reg(0) <= io_dq(0);`
596			`end if;`
597			`end if;`
598			`end if;`
599			`end if;`
600			`end if;`
601			`end process;`
602			`o_data_r <= data_r_reg;`
603
604			`-------------------------`
605			`-- SPI Read Data Valid --`
606			`-------------------------`
607			`process(i_sys_clock)`
608			`begin`
609			`if rising_edge(i_sys_clock) then`
610
611			`-- Clock Enable`
612			`if (i_sys_clock_en = '1') then`
613
614			`-- Data Read Ready`
615			`if (mem_mode_reg = MEM_READ_MODE) and (state = BYTES_TXRX) and (bit_counter_end = '1') then`
616			`data_r_ready_reg <= '1';`
617
618			`-- Data Read NOT Ready`
619			`else`
620			`data_r_ready_reg <= '0';`
621			`end if;`
622			`end if;`
623			`end if;`
624			`end process;`
625			`o_data_ready <= data_r_ready_reg;`
626
627			`----------------------`
628			`-- SPI Ready Status --`
629			`----------------------`
630			`o_ready <= '1' when state = IDLE else '0';`
631
632			`------------------`
633			`-- Reset Output --`
634			`------------------`
635			`o_reset <= not(i_reset);`
636
637			`---------------------------`
638			`-- SPI Slave Select Line --`
639			`---------------------------`
640			`o_ss <= DISABLE_SS_BIT when (state = IDLE) or (state = STOP_TX) else not(DISABLE_SS_BIT);`
641
642			`end Behavioral;`