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ldalmasso |
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-- Engineer: Dalmasso Loic
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-- Create Date: 19/02/2025
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-- Module Name: PmodSF3SPIFrequencyGenerator
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-- Description:
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-- Pmod SF3 SPI Frequency Generator for the 32 MB NOR Flash Memory MT25QL256ABA.
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-- From the System Input Clock, this module generate valid SPI Serial Clock Frequency according to the actual Dummy Cycles and SPI Mode (Single, Dual, Quad).
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-- If the wanted SPI Serial Clock Frequency cannot be generated (i.e., Specified SPI Flash Frequency > System Input Clock Frequency), the System Input Clock Frequency is used.
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-- When the System Input Clock Frequency is used, the 'o_using_sys_freq' signal is set.
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--
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-- SPI Frequency References (in MHz):
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-- | Dummy Cycles | Single SPI | Dual SPI | Quad SPI |
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-- | 0 | 133 | 94 | 133 |
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-- | 1 | 94 | 79 | 44 |
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-- | 2 | 112 | 97 | 61 |
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-- | 3 | 129 | 106 | 78 |
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-- | 4 | 133 | 115 | 97 |
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-- | 5 | 133 | 125 | 106 |
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-- | 6 | 133 | 133 | 115 |
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-- | 7 | 133 | 94 | 125 |
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-- | 8 | 133 | 94 | 133 |
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-- | 9 | 133 | 94 | 133 |
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-- | 10 | 133 | 94 | 133 |
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-- | 11 | 133 | 94 | 133 |
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-- | 12 | 133 | 94 | 133 |
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-- | 13 | 133 | 94 | 133 |
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-- | 14 | 133 | 94 | 133 |
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--
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-- Generics
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-- sys_clock: System Input Clock Frequency (Hz)
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--
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-- Ports
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-- Input - i_sys_clock: System Input Clock
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-- Input - i_reset: System Input Reset ('0': No Reset, '1': Reset)
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-- Input - i_spi_single_enable: Enable SPI Single Mode ('0': Disable, '1': Enable)
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-- Input - i_spi_dual_enable: Enable SPI Dual Mode ('0': Disable, '1': Enable)
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-- Input - i_dummy_cycles: Number of Dummy Cycles (0 to 14 cycles)
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-- Output - o_spi_freq: SPI Serial Clock Frequency
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-- Output - o_using_sys_freq: System Input Clock as SPI Serial Clock Frequency ('0': Disable, '1': Enable)
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------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE IEEE.MATH_REAL.ALL;
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ENTITY PmodSF3SPIFrequencyGenerator is
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GENERIC(
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sys_clock: INTEGER := 100_000_000
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);
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PORT(
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i_sys_clock: IN STD_LOGIC;
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i_reset: IN STD_LOGIC;
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i_spi_single_enable: IN STD_LOGIC;
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i_spi_dual_enable: IN STD_LOGIC;
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i_dummy_cycles: IN INTEGER range 0 to 15;
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o_spi_freq: OUT STD_LOGIC;
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o_using_sys_freq: OUT STD_LOGIC
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);
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END PmodSF3SPIFrequencyGenerator;
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ARCHITECTURE Behavioral of PmodSF3SPIFrequencyGenerator is
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------------------------------------------------------------------------
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-- Constant Declarations
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------------------------------------------------------------------------
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-- ROM Type
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type ROM_TYPE is array(INTEGER range 0 to 14) of INTEGER;
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-- No SPI Frequency Divider (use System Input Clock Frequency)
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constant NO_SPI_DIVIDER: INTEGER := 0;
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-- SPI Mode Frequency ROM Initialization
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function spi_mode_rom_initialization (rom_ref: ROM_TYPE) return ROM_TYPE is
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variable spi_freq: INTEGER;
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variable spi_freq_rom: ROM_TYPE;
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begin
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for index in INTEGER range 0 to 14 loop
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-- Get SPI Single Mode Frequency from ROM Reference (in MHz)
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spi_freq := rom_ref(index) * 1_000_000;
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-- Compare System Clock to ROM Reference
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if (spi_freq > sys_clock) then
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-- No Clock Divider
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spi_freq_rom(index) := NO_SPI_DIVIDER;
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else
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-- Clock Divider
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spi_freq_rom(index) := INTEGER((real(sys_clock) / real(spi_freq))) -1;
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end if;
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end loop;
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return spi_freq_rom;
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end spi_mode_rom_initialization;
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-- ROM Memories (Frequency Inputs in MHz)
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constant SINGLE_SPI_ROM: rom_type := spi_mode_rom_initialization(rom_ref => (133, 94, 112, 129, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133, 133));
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constant DUAL_SPI_ROM: rom_type := spi_mode_rom_initialization(rom_ref => (94, 79, 97, 106, 115, 125, 133, 94, 94, 94, 94, 94, 94, 94, 94));
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constant QUAD_SPI_ROM: rom_type := spi_mode_rom_initialization(rom_ref => (133, 44, 61, 78, 97, 106, 115, 125, 133, 133, 133, 133, 133, 133, 133));
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------------------------------------------------------------------------
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-- Signal Declarations
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------------------------------------------------------------------------
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-- SPI Clock Divider Reference
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signal spi_clock_div_ref: INTEGER := 0;
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-- SPI Clock Divider
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signal spi_clock_div: INTEGER := 0;
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-- SPI Serial Clock Frequency Register
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signal spi_freq_reg: STD_LOGIC := '0';
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------------------------------------------------------------------------
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-- Module Implementation
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------------------------------------------------------------------------
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begin
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------------------------
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-- SPI Clock Dividers --
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------------------------
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process(i_sys_clock)
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begin
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if rising_edge(i_sys_clock) then
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-- SPI Single Mode
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if (i_spi_single_enable = '1') then
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spi_clock_div_ref <= SINGLE_SPI_ROM(i_dummy_cycles);
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-- SPI Dual Mode
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elsif (i_spi_dual_enable = '1') then
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spi_clock_div_ref <= DUAL_SPI_ROM(i_dummy_cycles);
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-- SPI Quad Mode
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else
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spi_clock_div_ref <= QUAD_SPI_ROM(i_dummy_cycles);
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end if;
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end if;
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end process;
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-----------------------
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-- SPI Clock Counter --
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-----------------------
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process(i_sys_clock)
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begin
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if rising_edge(i_sys_clock) then
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-- Reset SPI Clock Divider
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if (i_reset = '1') or (spi_clock_div = 0) then
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spi_clock_div <= spi_clock_div_ref;
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-- Decrement SPI Clock Divider
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else
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spi_clock_div <= spi_clock_div -1;
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end if;
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end if;
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end process;
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--------------------------------
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-- SPI Serial Clock Frequency --
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--------------------------------
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process(i_sys_clock)
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begin
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if rising_edge(i_sys_clock) then
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-- Reset Frequency Register
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if (i_reset = '1') then
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spi_freq_reg <= '0';
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-- Set Frequency Register
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elsif (spi_clock_div = 0) then
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spi_freq_reg <= '1';
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else
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spi_freq_reg <= '0';
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end if;
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end if;
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end process;
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o_spi_freq <= spi_freq_reg;
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------------------------------------------------------
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-- System Input Clock as SPI Serial Clock Frequency --
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------------------------------------------------------
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process(i_sys_clock)
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begin
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if rising_edge(i_sys_clock) then
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-- SPI Clock Enable
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if (spi_clock_div_ref = NO_SPI_DIVIDER) then
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o_using_sys_freq <= '1';
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else
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o_using_sys_freq <= '0';
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end if;
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end if;
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end process;
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end Behavioral;
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