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**TWI Interrupt**
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**TWI Interrupt**
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The SPI module provides a single interrupt to signal "operation done" to the CPU. Whenever the TWI
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The SPI module provides a single interrupt to signal "operation done" to the CPU. Whenever the TWI
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module completes the current operation (generate stop condition, generate start conditions or transfer byte),
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module completes the current operation (generate stop condition, generate start conditions or transfer byte),
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the interrupt is triggered. Once triggered, the interrupt has to be explicitly cleared again by setting the according
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the interrupt is triggered. Once triggered, the interrupt has to be explicitly cleared again by
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`mip` CSR bit.
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writing zero to the according <<_mip>> CSR bit.
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.TWI register map (`struct NEORV32_TWI`)
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.TWI register map (`struct NEORV32_TWI`)
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[cols="<2,<2,<4,^1,<7"]
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[cols="<2,<2,<4,^1,<7"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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