URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_debug_dm.vhd] - Diff between revs 71 and 73

Rev 71	Rev 73
Line 679...	Line 679...
`begin`	`begin`
`if rising_edge(clk_i) then`	`if rising_edge(clk_i) then`
`-- Data buffer --`	`-- Data buffer --`
`if (dci.data_we = '1') then -- DM write access`	`if (dci.data_we = '1') then -- DM write access`
`data_buf <= dci.wdata;`	`data_buf <= dci.wdata;`
`elsif (acc_en = '1') and (maddr = "10") and (wren = '1') then -- BUS write access`	`elsif (maddr = "10") and (wren = '1') then -- BUS write access`
`data_buf <= cpu_data_i;`	`data_buf <= cpu_data_i;`
`end if;`	`end if;`
`-- Control and Status Register --`	`-- Control and Status Register --`
`dci.halt_ack <= '0'; -- all writable flags auto-clear`	`dci.halt_ack <= '0'; -- all writable flags auto-clear`
`dci.resume_ack <= '0';`	`dci.resume_ack <= '0';`
`dci.execute_ack <= '0';`	`dci.execute_ack <= '0';`
`dci.exception_ack <= '0';`	`dci.exception_ack <= '0';`
`if (acc_en = '1') and (maddr = "11") and (wren = '1') then`	`if (maddr = "11") and (wren = '1') then`
`dci.halt_ack <= cpu_data_i(sreg_halt_ack_c);`	`dci.halt_ack <= cpu_data_i(sreg_halt_ack_c);`
`dci.resume_ack <= cpu_data_i(sreg_resume_ack_c);`	`dci.resume_ack <= cpu_data_i(sreg_resume_ack_c);`
`dci.execute_ack <= cpu_data_i(sreg_execute_ack_c);`	`dci.execute_ack <= cpu_data_i(sreg_execute_ack_c);`
`dci.exception_ack <= cpu_data_i(sreg_exception_ack_c);`	`dci.exception_ack <= cpu_data_i(sreg_exception_ack_c);`
`end if;`	`end if;`