URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [bench/] [verilog/] [include/] [eth_stim.v] - Diff between revs 408 and 409

Rev 408	Rev 409
Line 45...	Line 45...

`// Defines for ethernet test to trigger sending/receiving`	`// Defines for ethernet test to trigger sending/receiving`
`// Is straight forward when using RTL design, but if using netlist then paths to`	`// Is straight forward when using RTL design, but if using netlist then paths to`
`// the RX/TX enabled bits depend on synthesis tool, etc, but ones here appear to`	`// the RX/TX enabled bits depend on synthesis tool, etc, but ones here appear to`
`// work with design put through Synplify, with hierarchy maintained.`	`// work with design put through Synplify, with hierarchy maintained.`
`define ETH_TOP dut.eth0	`define ETH_TOP dut.ethmac0
`define ETH_BD_RAM_PATH `ETH_TOP.wishbone.bd_ram	`define ETH_BD_RAM_PATH `ETH_TOP.wishbone.bd_ram
`define ETH_MODER_PATH `ETH_TOP.ethreg1.MODER_0	`define ETH_MODER_PATH `ETH_TOP.ethreg1.MODER_0

`ifdef RTL_SIM	`ifdef RTL_SIM
`ifdef eth_IS_GATELEVEL	`ifdef eth_IS_GATELEVEL