URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 584 |
Rev 620 |
Line 26... |
Line 26... |
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
|
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
|
|
|
void uart_init(void) {
|
void uart_init(void) {
|
int divisor;
|
int divisor;
|
|
|
|
/* Diable interrupt */
|
|
REG8(UART_BASE + UART_IER) = 0x0;
|
|
|
/* Reset receiver and transmiter */
|
/* Reset receiver and transmiter */
|
/* Set RX interrupt for each byte */
|
/* Set RX interrupt for each byte */
|
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
|
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
|
|
|
/* Enable RX interrupt */
|
/* Enable RX interrupt */
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.