URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_fnc_plugin/] [instructions.cpp] - Diff between revs 2 and 4

Rev 2	Rev 4
Line 1...	Line 1...
`/**`	`/**`
`* @file`	`* @file`
`* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.`	`* @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.`
`* @author Sergey Khabarov - sergeykhbr@gmail.com`	`* @author Sergey Khabarov - sergeykhbr@gmail.com`
`* @brief Instruction types parser.`	`* @brief Instruction types parser.`
`*/`	`*/`

`#include "api_utils.h"`	`#include "api_utils.h"`
`#include "riscv-isa.h"`	`#include "riscv-isa.h"`
`#include "instructions.h"`	`#include "instructions.h"`
	`#include "cpu_riscv_func.h"`

`namespace debugger {`	`namespace debugger {`

`unsigned addSupportedInstruction(IsaProcessor instr, AttributeType out) {`	`RiscvInstruction::RiscvInstruction(CpuRiver_Functional icpu, const char name,`
`AttributeType tmp(instr);`	`const char *bits) {`
`out[instr->hash()].add_to_list(&tmp);`	`icpu_ = icpu;`
`return 0;`	`R = icpu->getpRegs();`
	`name_.make_string(name);`
	`mask_ = 0;`
	`opcode_ = 0;`
	`for (int i = 0; i < 32; i++) {`
	`switch (bits[i]) {`
	`case '0':`
	`break;`
	`case '1':`
	`opcode_ \|= (1 << (31 - i));`
	`break;`
	`case '?':`
	`mask_ \|= (1 << (31 - i));`
	`break;`
	`default:;`
	`}`
	`}`
	`mask_ ^= ~0;`
`}`	`}`

`} // namespace debugger`	`} // namespace debugger`

`No newline at end of file`	`No newline at end of file`