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const uint8_t OPCODE_ADDW = 0x0E; // 01110: ADDW, SLLW, SRAW, SRLW, SUBW, DIVW, DIVUW, MULW, REMW, REMUW
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const uint8_t OPCODE_ADDW = 0x0E; // 01110: ADDW, SLLW, SRAW, SRLW, SUBW, DIVW, DIVUW, MULW, REMW, REMUW
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const uint8_t OPCODE_BEQ = 0x18; // 11000: BEQ, BNE, BLT, BGE, BLTU, BGEU
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const uint8_t OPCODE_BEQ = 0x18; // 11000: BEQ, BNE, BLT, BGE, BLTU, BGEU
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const uint8_t OPCODE_JALR = 0x19; // 11001: JALR
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const uint8_t OPCODE_JALR = 0x19; // 11001: JALR
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const uint8_t OPCODE_JAL = 0x1B; // 11011: JAL
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const uint8_t OPCODE_JAL = 0x1B; // 11011: JAL
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const uint8_t OPCODE_CSRR = 0x1C; // 11100: CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI, URET, SRET, HRET, MRET
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const uint8_t OPCODE_CSRR = 0x1C; // 11100: CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI, URET, SRET, HRET, MRET
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// Compressed instruction set
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const uint8_t OPCODE_C_ADDI4SPN = 0x00;
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const uint8_t OPCODE_C_NOP_ADDI = 0x01;
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const uint8_t OPCODE_C_SLLI = 0x02;
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const uint8_t OPCODE_C_JAL_ADDIW = 0x05;
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const uint8_t OPCODE_C_LW = 0x08;
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const uint8_t OPCODE_C_LI = 0x09;
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const uint8_t OPCODE_C_LWSP = 0x0A;
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const uint8_t OPCODE_C_LD = 0x0C;
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const uint8_t OPCODE_C_ADDI16SP_LUI = 0xD;
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const uint8_t OPCODE_C_LDSP = 0x0E;
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const uint8_t OPCODE_C_MATH = 0x11;
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const uint8_t OPCODE_C_JR_MV_EBREAK_JALR_ADD = 0x12;
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const uint8_t OPCODE_C_J = 0x15;
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const uint8_t OPCODE_C_SW = 0x18;
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const uint8_t OPCODE_C_BEQZ = 0x19;
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const uint8_t OPCODE_C_SWSP = 0x1A;
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const uint8_t OPCODE_C_SD = 0x1C;
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const uint8_t OPCODE_C_BNEZ = 0x1D;
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const uint8_t OPCODE_C_SDSP = 0x1E;
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SC_MODULE(InstrDecoder) {
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SC_MODULE(InstrDecoder) {
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sc_in<bool> i_clk;
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sc_in<bool> i_clk;
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sc_in<bool> i_nrst; // Reset active low
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sc_in<bool> i_nrst; // Reset active low
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sc_in<bool> i_any_hold; // Hold pipeline by any reason
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sc_in<bool> i_any_hold; // Hold pipeline by any reason
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Line 61... |
sc_out<bool> o_memop_store; // Store to memory operation
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sc_out<bool> o_memop_store; // Store to memory operation
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sc_out<bool> o_memop_load; // Load from memoru operation
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sc_out<bool> o_memop_load; // Load from memoru operation
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sc_out<bool> o_memop_sign_ext; // Load memory value with sign extending
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sc_out<bool> o_memop_sign_ext; // Load memory value with sign extending
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sc_out<sc_uint<2>> o_memop_size; // Memory transaction size
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sc_out<sc_uint<2>> o_memop_size; // Memory transaction size
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sc_out<bool> o_rv32; // 32-bits instruction
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sc_out<bool> o_rv32; // 32-bits instruction
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sc_out<bool> o_compressed; // C-type instruction
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sc_out<bool> o_unsigned_op; // Unsigned operands
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sc_out<bool> o_unsigned_op; // Unsigned operands
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sc_out<sc_bv<ISA_Total>> o_isa_type; // Instruction format accordingly with ISA
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sc_out<sc_bv<ISA_Total>> o_isa_type; // Instruction format accordingly with ISA
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sc_out<sc_bv<Instr_Total>> o_instr_vec; // One bit per decoded instruction bus
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sc_out<sc_bv<Instr_Total>> o_instr_vec; // One bit per decoded instruction bus
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sc_out<bool> o_exception;
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sc_out<bool> o_exception;
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sc_signal<bool> memop_load;
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sc_signal<bool> memop_load;
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sc_signal<bool> memop_sign_ext;
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sc_signal<bool> memop_sign_ext;
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sc_signal<sc_uint<2>> memop_size;
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sc_signal<sc_uint<2>> memop_size;
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sc_signal<bool> unsigned_op;
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sc_signal<bool> unsigned_op;
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sc_signal<bool> rv32;
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sc_signal<bool> rv32;
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sc_signal<bool> compressed;
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sc_signal<bool> instr_unimplemented;
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sc_signal<bool> instr_unimplemented;
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} v, r;
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} v, r;
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};
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};
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