URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [core/] [fetch.cpp] - Diff between revs 3 and 4

Rev 3	Rev 4
Line 75...	Line 75...
`w_o_mem_resp_ready = !i_pipeline_hold.read();`	`w_o_mem_resp_ready = !i_pipeline_hold.read();`
`w_resp_fire = i_mem_data_valid.read() && w_o_mem_resp_ready;`	`w_resp_fire = i_mem_data_valid.read() && w_o_mem_resp_ready;`

`w_predict_miss = 1;`	`w_predict_miss = 1;`
`if (i_e_npc == r.pc_z1`	`if (i_e_npc == r.pc_z1`
`\|\| i_e_npc == i_predict_npc \|\| i_e_npc == r.raddr_not_resp_yet) {`	`\|\| i_e_npc == r.raddr_not_resp_yet) {`
`w_predict_miss = 0;`	`w_predict_miss = 0;`
`}`	`}`

`if (w_predict_miss) {`	`if (w_predict_miss) {`
`wb_o_addr_req = i_e_npc.read();`	`wb_o_addr_req = i_e_npc.read();`