URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [core/] [proc.h] - Diff between revs 3 and 4

Rev 3	Rev 4
Line 92...	Line 92...
`sc_signal<bool> memop_store;`	`sc_signal<bool> memop_store;`
`sc_signal<bool> memop_load;`	`sc_signal<bool> memop_load;`
`sc_signal<bool> memop_sign_ext;`	`sc_signal<bool> memop_sign_ext;`
`sc_signal<sc_uint<2>> memop_size;`	`sc_signal<sc_uint<2>> memop_size;`
`sc_signal<bool> rv32; // 32-bits instruction`	`sc_signal<bool> rv32; // 32-bits instruction`
	`sc_signal<bool> compressed; // C-extension`
`sc_signal<bool> unsigned_op; // Unsigned operands`	`sc_signal<bool> unsigned_op; // Unsigned operands`
`sc_signal<sc_bv<ISA_Total>> isa_type;`	`sc_signal<sc_bv<ISA_Total>> isa_type;`
`sc_signal<sc_bv<Instr_Total>> instr_vec;`	`sc_signal<sc_bv<Instr_Total>> instr_vec;`
`sc_signal<bool> exception;`	`sc_signal<bool> exception;`
`};`	`};`