URL
https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk
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Line 63... |
Line 63... |
RegsArrType regarr;
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RegsArrType regarr;
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uint8_t buf[sizeof(RegsArrType)];
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uint8_t buf[sizeof(RegsArrType)];
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} t1;
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} t1;
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DsuMapType *dsu = info_->getpDsu();
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DsuMapType *dsu = info_->getpDsu();
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uint64_t addr = reinterpret_cast<uint64_t>(dsu->ureg.v.iregs);
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uint64_t addr = reinterpret_cast<uint64_t>(dsu->ureg.v.iregs);
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addr &= 0xFFFFFFFFul;
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tap_->read(addr, 8 * soclst.size(), t1.buf);
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tap_->read(addr, 8 * soclst.size(), t1.buf);
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uint64_t idx;
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res->make_dict();
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res->make_dict();
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for (unsigned i = 0; i < soclst.size(); i++) {
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for (unsigned i = 0; i < soclst.size(); i++) {
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const char *name = soclst[i].to_string();
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const char *name = soclst[i].to_string();
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(*res)[name].make_uint64(t1.regarr.reg[i].val);
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if (strlen(name) == 0) {
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continue;
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}
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idx = (info_->reg2addr(name) - addr) / sizeof(uint64_t);
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(*res)[name].make_uint64(t1.regarr.reg[idx].val);
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}
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}
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}
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}
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} // namespace debugger
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} // namespace debugger
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