URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testBaud_generator.vhd] - Diff between revs 11 and 36

Rev 11	Rev 36
Line 35...	Line 35...
`-- Clock period definitions (1.8432MHz)`	`-- Clock period definitions (1.8432MHz)`
`constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)`	`constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)`

`BEGIN`	`BEGIN`

`-- Instantiate the Unit Under Test (UUT)`	`--! Instantiate the Unit Under Test (UUT)`
`uut: baud_generator PORT MAP (`	`uut: baud_generator PORT MAP (`
`rst => rst,`	`rst => rst,`
`clk => clk,`	`clk => clk,`
`cycle_wait => cycle_wait,`	`cycle_wait => cycle_wait,`
`baud_oversample => baud_oversample,`	`baud_oversample => baud_oversample,`