URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 147 and 148

Rev 147	Rev 148
Line 3435...	Line 3435...
`.q_b(rd2mem),`	`.q_b(rd2mem),`
`.adr_b(a2),`	`.adr_b(a2),`
`.clk_b(clk) );`	`.clk_b(clk) );`
`always @ (posedge clk or posedge rst)`	`always @ (posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
`{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};`	`{sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}};`
`else`	`else`
`{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};`	`{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};`
`assign rd1 = (sel1) ? wreg : rd1mem;`	`assign rd1 = (sel1) ? wreg : rd1mem;`
`assign rd2 = (sel2) ? wreg : rd2mem;`	`assign rd2 = (sel2) ? wreg : rd2mem;`
`endmodule`	`endmodule`