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[/] - Rev 100
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Last modification
- Rev 100 2004-05-21 11:47:48 GMT
- Author: tadejm
- Log message:
- Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs.