URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] - Rev 11

Rev	Log message	Author	Age	Path
11	Corrected a small problem with the KAT testbench.	motilito	4351d 22h	/
10	Minor documentation bug fix.	motilito	4713d 09h	/
9	Corrected block diagram with the size of i_key_mode input signal.	motilito	4752d 10h	/
8	Added core specification document, core top example module and FPGA synthesis project files.	motilito	4752d 21h	/
7	Added AES KAT test bench and simulation batch files for Icarus Verilog. Note that reset polarity was changed to rising edge (posedge).	motilito	5207d 20h	/
6	Correcting some problems with bench directory	motilito	5208d 00h	/
5	Updating sub-directory structure	motilito	5208d 00h	/
4	Moving RTL to verilog sub-directory	motilito	5208d 00h	/
3	Building new directory structure.	motilito	5208d 10h	/
2	initial release	rainrhythm	5509d 16h	/
1	The project and the structure was created	root	5512d 02h	/