URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] - Rev 25

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Rev	Log message	Author	Age	Path
25	Adding some sample code on the doc folder, also adding the wishbone public domain library file	leonardoaraujo.santos	4724d 07h	/
24	Working on testbench and refactoring... now we could start some tests on the board...	leonardoaraujo.santos	4725d 05h	/
23	Working on uart_control refactoring	leonardoaraujo.santos	4725d 06h	/
22	Refactoring the uart_control	leonardoaraujo.santos	4725d 09h	/
21	Preparing to rewrite uart_control, adding pin to indicate data available at the RX	leonardoaraujo.santos	4725d 15h	/
20	Finishing at least the tests on testbench.... Was good to verify that the uart_control should be redesigned to allow concurrent receive and to clean the code...	leonardoaraujo.santos	4725d 23h	/
19	Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd)	leonardoaraujo.santos	4726d 00h	/
18	sdsd	leonardoaraujo.santos	4726d 07h	/
17	Working on slave testbench and fixing some bugs	leonardoaraujo.santos	4726d 08h	/
16	Adding testbench for wishbone slave module	leonardoaraujo.santos	4726d 08h	/
15	Taking out some warnings and transparent latches from the design	leonardoaraujo.santos	4726d 10h	/
14	Fixing some warnings... Adding wishbone slave	leonardoaraujo.santos	4727d 05h	/
13	Working on uart_control testbench... also applying some fixes...	leonardoaraujo.santos	4727d 06h	/
12	Working on the communication blocks	leonardoaraujo.santos	4727d 07h	/
11	Adding uart_communication_block	leonardoaraujo.santos	4727d 10h	/
10	Working on the control unit part	leonardoaraujo.santos	4727d 14h	/
9	Adding Control unit for uart block	leonardoaraujo.santos	4728d 01h	/
8	Solving some bugs in baud_generator.vhd	leonardoaraujo.santos	4728d 12h	/
7	Remember to clean project files	leonardoaraujo.santos	4729d 08h	/
6	Adding baud generator	leonardoaraujo.santos	4729d 08h	/

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Subversion Repositories uart_block

[/] - Rev 25

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