URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [sim/] [rtl_sim/] [bin/] [nc.scr] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5883d 02h	/uart16550/trunk/sim/rtl_sim/bin/nc.scr
83	Reverted to include uart_defines.v file in other files again.	gorban	8298d 14h	/uart16550/trunk/sim/rtl_sim/bin/nc.scr
82	Updated to work with latest core.	gorban	8305d 12h	/uart16550/trunk/sim/rtl_sim/bin/nc.scr
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8533d 21h	/uart16550/trunk/sim/rtl_sim/bin/nc.scr
14		gorban	8649d 19h	/uart16550/trunk/sim/rtl_sim/bin/nc.scr